The HIPERLAN Equalizer ASIC Complexity and its Relationship With the Training Header

In this document, an attempt is made to estimate the size of the HIPERLAN equalizer ASIC by extrapolating from existing adaptive equalizer ASICs and making certain assumptions regarding the process and methodology used to design the HIPERLAN equalizer. Two scenarios are considered, first, an equalizer using the LMS algorithm every baud to update the tap coefficients and second, an equalizer using an RLS algorithm performing a set of updates every ten baud intervals. It was discovered that the computational complexity of both approaches are within the same order of magnitude, however, the LMS ASIC will occupy at most half the size of its RLS counterpart. The smaller IC will reduce the overall system cost at the expense of the longer convergence time required by the LMS algorithm. The paper also demonstrates that when the overall packet processing delay is taken into account, the slower-converging and cheaper LMS type equalizer will actually produce faster turn-around times for short packets than its RLS counter part. Thus, a new training header length is suggested that would allow vendors some flexibility in choosing the structure that best suites their product