PAFSV: A Formal Framework for Specification and Analysis of SystemVerilog

We develop a process algebraic framework PAFSV for the formal specification and analysis of IEEE 1800TM SystemVerilog designs. The formal semantics of PAFSV is defined by means of deduction rules that associate a time transition system with a PAFSV process. A set of properties of PAFSV is presented for a notion of bisimilarity. PAFSV may be regarded as the formal language of a significant subset of IEEE 1800TM SystemVerilog. To show that PAFSV is useful for the formal specification and analysis of IEEE 1800TM SystemVerilog designs, we illustrate the use of PAFSV with a multiplexer, a synchronous reset D flip-flop and an arbiter

The Formal Simulation Semantics of SystemVerilog

We present a rigorous but transparent semantics definition of SystemVerilog that covers processes with blocking and non-blocking statements as well as their interaction with the simulation scheduler including the management of new SystemVerilog regions. We present our definition in form of distributed Abstract State Machines (ASMs) rules reflecting the view given in the SystemVerilog Language Reference Manual [1]. Our formal semantics is a concise, unambiguous, high-level specification for SystemVerilog-based implementations and for investigation of interoperabilities of SystemVerilog with SpecC, SystemC, and VHDL. 1