Testing Domino Circuits in SOI Technology

The proliferation of both Partially Depleted SiliconOn -Insulator (PD-SOI) technology and domino circuit styles has allowed for increases in circuit performance beyond that of scaling traditional bulk CMOS static circuits. However, interactions between dynamic circuit styles and PD-SOI complicate testing. This paper describes the issues of testing domino circuits fabricated in SOI technology and new tests are proposed to address the interactions. A fault modeling analysis is described which demonstrates that the overall fault coverage can be improved beyond that of traditional testing of domino circuits in bulk technology. 1. Introduction Partially-Depleted Silicon-On-Insulator technology has become a leading candidate for replacing traditional bulk CMOS as the dominant processing vehicle for high performance / low power VLSI designs. Based on the significant reduction in junction capacitance of the individual transistor, SOI provides a reduction in delay or a corresponding reduction..