Development of helicopter attitude axes controlled hover flight without pilot assistance and vehicle crashes.

In this work, we show how to computerize a helicopter to fly attitude axes controlled hover flight without the assistance of a pilot and without ever crashing. We start by developing a helicopter research test bed system including all hardware, software, and means for testing and training the helicopter to fly by computer. We select a Remote Controlled helicopter with a 5 ft. diameter rotor and 2.2 hp engine. We equip the helicopter with a payload of sensors, computers, navigation and telemetry equipment, and batteries. We develop a differential GPS system with cm accuracy and a ground computerized navigation system for six degrees of freedom (6-DoF) free flight while tracking navigation commands. We design feedback control loops with yet-to-be-determined gains for the five control "knobs" available to a flying radio-controlled (RC) miniature helicopter: engine throttle, main rotor collective pitch, longitudinal cyclic pitch, lateral cyclic pitch, and tail rotor collective pitch.We develop helicopter flight equations using fundamental dynamics, helicopter momentum theory and blade element theory. The helicopter flight equations include helicopter rotor equations of motions, helicopter rotor forces and moments, helicopter trim equations, helicopter stability derivatives, and a coupled fuselage-rotor helicopter 6-DoF model. The helicopter simulation also includes helicopter engine control equations, a helicopter aerodynamic model, and finally helicopter stability and control equations. The derivation of a set of non-linear equations of motion for the main rotor is a contribution of this thesis work.After discussing the integration of hardware and software elements of our helicopter research test bed system, we perform a number of experiments and tests using the two specially built test stands. Feedback gains are derived for controlling the following: (1) engine throttle to maintain prescribed main rotor angular speed, (2) main rotor collective pitch to maintain constant elevation, (3) longitudinal cyclic pitch to maintain prescribed pitch angle, (4) lateral cyclic pitch to maintain prescribed roll angle, and (5) yaw axis to maintain prescribed compass direction. (Abstract shortened by UMI.)We design and build two special test stands for training and testing the helicopter to fly attitude axes controlled hover flight, starting with one axis at a time and progressing to multiple axes. The first test stand is built for teaching and testing controlled flight of elevation and yaw (i.e., directional control). The second test stand is built for teaching and testing any one or combination of the following attitude axes controlled flight: (1) pitch, (2) roll and (3) yaw. The subsequent development of a novel method to decouple, stabilize and teach the helicopter hover flight is a primary contribution of this thesis.The novel method included the development of a non-linear modeling technique for linearizing the RPM state equation dynamics so that a simple but accurate transfer function is derivable between the "available torque of the engine" and RPM. Specifically, the main rotor and tail rotor torques are modeled accurately with a bias term plus a nonlinear term involving the product of RPM squared times the main rotor blade pitch angle raised to the three-halves power. Application of this non-linear modeling technique resulted in a simple, representative and accurate transfer function model of the open-loop plant for the entire helicopter system so that all the feedback control laws for autonomous flight purposes could be derived easily using classical control theory. This is one of the contributions of this dissertation work

High Level Synthesis of Neural Network Chips

This thesis investigates the development of a silicon compiler dedicated to generate Application-Specific Neural Network Chips (ASNNCs) from a high level C-based behavioural specification language. The aim is to fully integrate the silicon compiler with the ESPRIT II Pygmalion neural programming environment. The integration of these two tools permits the translation of a neural network application specified in nC, the Pygmalion's C-based neural programming language, into either binary (for simulation) or silicon (for execution in hardware). Several applications benefit from this approach, in particular the ones that require real-time execution, for which a true neural computer is required. This research comprises two major parts: extension of the Pygmalion neural programming environment, to support automatic generation of neural network chips from the nC specification language; and implementation of the high level synthesis part of the neural silicon compiler. The extension of the neural programming environment has been developed to adapt the nC language to hardware constraints, and to provide the environment with a simulation tool to test in advance the performance of the neural chips. Firstly, new hardware-specific requisites have been incorporated to nC. However, special attention has been taken to avoid transforming nC into a hardware-oriented language, since the system assumes minimum (or even no) knowledge of VLSI design from the application developer. Secondly, a simulator for neural network hardware has been developed, which assesses how well the generated circuit will perform the neural computation. Lastly, a hardware library of neural network models associated with a target VLSI architecture has been built. The development of the neural silicon compiler focuses on the high level synthesis part of the process. The goal of the silicon compiler is to take nC as the input language and automatically translate it into one or more identical integrated circuits, which are specified in VHDL (the IEEE standard hardware description language) at the register transfer level. The development of the high level synthesis comprises four major parts: firstly, compilation and software-like optimisations of nC; secondly, transformation of the compiled code into a graph-based internal representation, which has been designed to be the basis for the hardware synthesis; thirdly, further transformations and hardware-like optimisations on the internal representation; and finally, creation of the neural chip's data path and control unit that implement the behaviour specified in nC. Special attention has been devoted to the creation of optimised hardware structures for the ASNNCs employing both phases of neural computing on-chip: recall and learning. This is achieved through the data path and control synthesis algorithms, which adopt a heuristic approach that targets the generated hardware structure of the neural chip in a specific VLSI architecture, namely the Generic Neuron. The viability, concerning the effective use of silicon area versus speed, has been evaluated through the automatic generation of a VHDL description for the neural chip employing the Back Propagation neural network model. This description is compared with the one created manually by a hardware designer