6 research outputs found
Design-for-delay-testability techniques for high-speed digital circuits
The importance of delay faults is enhanced by the ever increasing clock rates and decreasing geometry sizes of nowadays' circuits. This thesis focuses on the development of Design-for-Delay-Testability (DfDT) techniques for high-speed circuits and embedded cores. The rising costs of IC testing and in particular the costs of Automatic Test Equipment are major concerns for the semiconductor industry. To reverse the trend of rising testing costs, DfDT is\ud
getting more and more important
Fault modeling, delay evaluation and path selection for delay test under process variation in nano-scale VLSI circuits
Delay test in nano-scale VLSI circuits becomes more difficult with shrinking
technology feature sizes and rising clock frequencies. In this dissertation, we study three
challenging issues in delay test: fault modeling, variational delay evaluation and path
selection under process variation. Previous research of fault modeling on resistive spot
defects, such as resistive opens and bridges in the interconnect, and resistive shorts in
devices, lacked an accurate fault model. As a result it was difficult to perform fault
simulation and select the best vectors. Conventional methods to compute variational delay
under process variation are either slow or inaccurate. On the problem of path selection
under process variation, previous approaches either choose too many paths, or missed the
path that is necessary to be tested.
We present new solutions in this dissertation. A new fault model that clearly and
comprehensively expresses the relationship between electrical behaviors and resistive
spots is proposed. Then the effect of process variations on path delays is modeled with a
linear function and a fast method to compute coefficients of the linear function is also
derived. Finally, we present the new path pruning algorithms that efficiently prune unimportant paths for test, and as a result we select as few as possible paths for test while
the fault coverage is satisfied. The experimental results show that the new solutions are
efficient and accurate
Investigation into voltage and process variation-aware manufacturing test
Increasing integration and complexity in IC design provides challenges for manufacturing testing. This thesis studies how process and supply voltage variation influence defect behaviour to determine the impact on manufacturing test cost and quality. The focus is on logic testing of static CMOS designs with respect to two important defect types in deep submicron CMOS: resistive bridges and full opens. The first part of the thesis addresses testing for resistive bridge defects in designs with multiple supply voltage settings. To enable analysis, a fault simulator is developed using a supply voltage-aware model for bridge defect behaviour. The analysis shows that for high defect coverage it is necessary to perform test for more than one supply voltage setting, due to supply voltage-dependent behaviour. A low-cost and effective test method is presented consisting of multi-voltage test generation that achieves high defect coverage and test set size reduction without compromise to defect coverage. Experiments on synthesised benchmarks with realistic bridge locations validate the proposed method.The second part focuses on the behaviour of full open defects under supply voltage variation. The aim is to determine the appropriate value of supply voltage to use when testing. Two models are considered for the behaviour of full open defects with and without gate tunnelling leakage influence. Analysis of the supply voltage-dependent behaviour of full open defects is performed to determine if it is required to test using more than one supply voltage to detect all full open defects. Experiments on synthesised benchmarks using an extended version of the fault simulator tool mentioned above, measure the quantitative impact of supply voltage variation on defect coverage.The final part studies the impact of process variation on the behaviour of bridge defects. Detailed analysis using synthesised ISCAS benchmarks and realistic bridge model shows that process variation leads to additional faults. If process variation is not considered in test generation, the test will fail to detect some of these faults, which leads to test escapes. A novel metric to quantify the impact of process variation on test quality is employed in the development of a new test generation tool, which achieves high bridge defect coverage. The method achieves a user-specified test quality with test sets which are smaller than test sets generated without consideration of process variation
High Quality Compact Delay Test Generation
Delay testing is used to detect timing defects and ensure that a circuit meets its
timing specifications. The growing need for delay testing is a result of the advances in
deep submicron (DSM) semiconductor technology and the increase in clock frequency.
Small delay defects that previously were benign now produce delay faults, due to
reduced timing margins. This research focuses on the development of new test methods
for small delay defects, within the limits of affordable test generation cost and pattern
count.
First, a new dynamic compaction algorithm has been proposed to generate
compacted test sets for K longest paths per gate (KLPG) in combinational circuits or
scan-based sequential circuits. This algorithm uses a greedy approach to compact paths
with non-conflicting necessary assignments together during test generation. Second, to
make this dynamic compaction approach practical for industrial use, a recursive learning
algorithm has been implemented to identify more necessary assignments for each path,
so that the path-to-test-pattern matching using necessary assignments is more accurate.
Third, a realistic low cost fault coverage metric targeting both global and local delay
faults has been developed. The metric suggests the test strategy of generating a different
number of longest paths for each line in the circuit while maintaining high fault coverage.
The number of paths and type of test depends on the timing slack of the paths under this
metric. Experimental results for ISCAS89 benchmark circuits and three industry circuits
show that the pattern count of KLPG can be significantly reduced using the proposed
methods. The pattern count is comparable to that of transition fault test, while achieving
higher test quality. Finally, the proposed ATPG methodology has been applied to an
industrial quad-core microprocessor. FMAX testing has been done on many devices and
silicon data has shown the benefit of KLPG test
Fault simulation and test generation for small delay faults
Delay faults are an increasingly important test challenge. Traditional delay fault
models are incomplete in that they model only a subset of delay defect behaviors. To
solve this problem, a more realistic delay fault model has been developed which models
delay faults caused by the combination of spot defects and parametric process variation.
According to the new model, a realistic delay fault coverage metric has been developed.
Traditional path delay fault coverage metrics result in unrealistically low fault coverage,
and the real test quality is not reflected. The new metric uses a statistical approach and the
simulation based fault coverage is consistent with silicon data. Fast simulation algorithms
are also included in this dissertation.
The new metric suggests that testing the K longest paths per gate (KLPG) has high
detection probability for small delay faults under process variation. In this dissertation, a
novel automatic test pattern generation (ATPG) methodology to find the K longest
testable paths through each gate for both combinational and sequential circuits is
presented. Many techniques are used to reduce search space and CPU time significantly.
Experimental results show that this methodology is efficient and able to handle circuits with an exponential number of paths, such as ISCAS85 benchmark circuit c6288.
The ATPG methodology has been implemented on industrial designs. Speed binning
has been done on many devices and silicon data has shown significant benefit of the
KLPG test, compared to several traditional delay test approaches
Abstract Test Generation for Global Delay Faults
This paper describes test generation for delay faults caused by global process disturbances. The structural and spatial correlation between path delays is used to reduce the number of paths that must be tested. Results are given for the ISCAS85 benchmarks