Technology-dependent Transformations For Low-power Synthesis

We propose a methodology for applying gate-level logic transformations to optimize power in digital circuits. Statistically simulated[14] switching information, gate delays, signal arrival patterns, and signal probabilities are considered in reducing the switching activity-capacitance products. Power reduction up to 45.4% (average 12.4%) is achieved, with considerable improvements in area and delay, in preoptimized benchmarks. Also the e#ect of transformations on the random pattern testability of the circuits is studied. 1. Introduction Power reduction has become an important objective at every level of digital circuit design. The problem of power optimization has been considered at the system[12] and architecture [2] levels. In this paper, we address the problem at the logic synthesis level. Like the classical area and delay optimization approaches, power optimization also has been attempted through technology-dependent and technologyindependent methods. The technology-independent m..