The future of computing beyond Moore's Law.

Moore's Law is a techno-economic model that has enabled the information technology industry to double the performance and functionality of digital electronics roughly every 2 years within a fixed cost, power and area. Advances in silicon lithography have enabled this exponential miniaturization of electronics, but, as transistors reach atomic scale and fabrication costs continue to rise, the classical technological driver that has underpinned Moore's Law for 50 years is failing and is anticipated to flatten by 2025. This article provides an updated view of what a post-exascale system will look like and the challenges ahead, based on our most recent understanding of technology roadmaps. It also discusses the tapering of historical improvements, and how it affects options available to continue scaling of successors to the first exascale machine. Lastly, this article covers the many different opportunities and strategies available to continue computing performance improvements in the absence of historical technology drivers. This article is part of a discussion meeting issue 'Numerical algorithms for high-performance computational science'

3D Multi-Subband Ensemble Monte Carlo Simulator of FinFETs and nanowire transistors

In this paper we present the development of a 3D Multi Subband Ensemble Monte Carlo (3DMSB-EMC) tool targeting the simulation of nanoscaled FinFETs and nanowire transistors. In order to deliver computational efficiency, we have developed a self-consistent framework that couples a MSB- EMC transport engine for a 1D electron gas with a 3DPoisson- 2DSchro ̈dinger solver. Here we use a FinFET with a physical channel length of 15nm as an example to demonstrate the appli- cability and highlight the benefits of the simulation framework. A comparison of the 3DMSB-EMC with Non-Equilibrium Green’s Functions (NEGFs) in the ballistic limit is used to verify and validate our approach

Development and Flight Results from the C3D2 Imager Payload on AlSat Nano

An experimental CubeSat camera system using 3 separate CMOS imagers was flown in 2014 on UKube-1. In response to an announcement opportunity in December 2014, we proposed an upgrade to our C3D imager payload, which was accepted to fly on AlSat Nano. Launched in September 2016 the system has been operational for over 1 year and has returned both images and housekeeping data, including detailed temperature and radiation dosimetry measurements. Through these in-orbit demonstrations on CubeSans, the image sensors and payload have attained TRL9, and these are now being used in other flight opportunities. In this paper we describe the C3D imager payload, which comprises 3 independent CMOS image sensors used in different camera systems; two wide field cameras are specifically optimised with one to observe the Earth from the 650 km orbit, and the other with its focus set to 40 cm to observe a deployable boom from the CubeSat. The experiment controller also contained thermometry and two RADFET dosimeters, one located on the payload, with the other deployed at a different point on the spacecraft. In this paper we will describe the experiment design and operational performance, and review the in-orbit data obtained during the operations covering over 17 months in-orbit, in addition to discussing lessons learned from the flight experience. We also discuss further developments of the payload concept which we are currently working on toward future flight opportunities

R&D Paths of Pixel Detectors for Vertex Tracking and Radiation Imaging

This report reviews current trends in the R&D of semiconductor pixellated sensors for vertex tracking and radiation imaging. It identifies requirements of future HEP experiments at colliders, needed technological breakthroughs and highlights the relation to radiation detection and imaging applications in other fields of science.Comment: 17 pages, 2 figures, submitted to the European Strategy Preparatory Grou

On evolution of CMOS image sensors

CMOS Image Sensors have become the principal technology in majority of digital cameras. They started replacing the film and Charge Coupled Devices in the last decade with the promise of lower cost, lower power requirement, higher integration and the potential of focal plane processing. However, the principal factor behind their success has been the ability to utilise the shrinkage in CMOS technology to make smaller pixels, and thereby have more resolution without increasing the cost. With the market of image sensors exploding courtesy their inte- gration with communication and computation devices, technology developers improved the CMOS processes to have better optical performance. Nevertheless, the promises of focal plane processing as well as on-chip integration have not been fulfilled. The market is still being pushed by the desire of having higher number of pixels and better image quality, however, differentiation is being difficult for any image sensor manufacturer. In the paper, we will explore potential disruptive growth directions for CMOS Image sensors and ways to achieve the same

MIDAS: Automated Approach to Design Microwave Integrated Inductors and Transformers on Silicon

The design of modern radiofrequency integrated circuits on silicon operating at microwave and millimeter-waves requires the integration of several spiral inductors and transformers that are not commonly available in the process design-kits of the technologies. In this work we present an auxiliary CAD tool for Microwave Inductor (and transformer) Design Automation on Silicon (MIDAS) that exploits commercial simulators and allows the implementation of an automatic design flow, including three-dimensional layout editing and electromagnetic simulations. In detail, MIDAS allows the designer to derive a preliminary sizing of the inductor (transformer) on the bases of the design entries (specifications). It draws the inductor (transformer) layers for the specific process design kit, including vias and underpasses, with or without patterned ground shield, and launches the electromagnetic simulations, achieving effective design automation with respect to the traditional design flow for RFICs. With the present software suite the complete design time is reduced significantly (typically 1 hour on a PC based on Intel® Pentium® Dual 1.80GHz CPU with 2-GB RAM). Afterwards both the device equivalent circuit and the layout are ready to be imported in the Cadence environment

A Graphene Field-Effect Device

In this letter, a top-gated field effect device (FED) manufactured from monolayer graphene is investigated. Except for graphene deposition, a conventional top-down CMOS-compatible process flow is applied. Carrier mobilities in graphene pseudo-MOS structures are compared to those obtained from top-gated Graphene-FEDs. The extracted values exceed the universal mobility of silicon and silicon-on-insulator MOSFETs.Comment: 12 pages, 3 figure