Technology Mapping for Electrically Programmable Gate Arrays

We describe a new approach for technology mapping of electrically programmable gate arrays (EPGAs). These are arrays of uncommitted modules, where the personalization is achieved by fuse/antifuse technology and can be modeled by stuck-at and/or bridging inputs. We present a matching algorithm that determines whether a portion of a combinational logic circuit can be implemented by personalizing a module. The algorithm has the advantage of considering the entire library of functions that can be implemented by the module without resorting to an explicit enumeration. The benefits are an increased efficiency in technology mapping, as well as portability to different types of electrically programmable gate arrays. Experimental results on standard benchmarks are reported