A Multiprocessor three-dimensional graphics systems.

by Hui Chau Man.Thesis (M.Phil.)--Chinese University of Hong Kong, 1991.Includes bibliographical references.ABSTRACT --- p.iACKNOWLEDGEMENTS --- p.iiTABLE OF CONTENTS --- p.iiiChapter CHAPTER 1 --- INTRODUCTIONChapter 1.1 --- Computer Graphics Today --- p.2Chapter 1.1.1 --- 3D Graphics Synthesis Techniques --- p.2Chapter 1.1.2 --- Hardware-assisted Computer Graphics --- p.4Chapter 1.2 --- About The Thesis --- p.5Chapter CHAPTER 2 --- GRAPHICS SYSTEM ARCHITECTURESChapter 2.1 --- Basic Structure of a Graphics Subsystem --- p.8Chapter 2.2 --- VLSI Graphics Chips --- p.9Chapter 2.2.1 --- The CRT Controllers --- p.10Chapter 2.2.2 --- The VLSI Graphics Processors --- p.11Chapter 2.2.3 --- Design Philosophies for VLSI Graphics Processors --- p.12Chapter 2.3 --- Graphics Boards --- p.14Chapter 2.3.1 --- The ARTIST 10 Graphics Controller --- p.14Chapter 2.3.2 --- The MATROX PG-1281 Graphics Controller --- p.16Chapter 2.4 --- High-end Graphics System Architectures --- p.17Chapter 2.4.1 --- Graphics Accelerator with Multiple Functional Units --- p.18Chapter 2.4.2 --- Parallel Processing Graphics Systems --- p.18Chapter 2.4.3 --- The Parallel Processor Architecture --- p.19Chapter 2.4.4 --- The Pipelined Architecture --- p.21Chapter 2.5 --- Comparisons and Discussions --- p.22Chapter 2.5.1 --- Parallel Processors versus Pipelined Processing --- p.23Chapter 2.5.2 --- Parallel Processors versus Multiple Functional Units --- p.23Chapter 2.6 --- Summary of High-end Graphics Systems --- p.24Chapter CHAPTER 3 --- AN ISA 3D GRAPHICS DISPLAY SERVERChapter 3.1 --- Common ISA Graphics Cards --- p.26Chapter 3.1.1 --- Standard Video Display Cards --- p.26Chapter 3.1.2 --- Graphics Processing Boards --- p.27Chapter 3.2 --- A Depth Processor for the ISA computers --- p.28Chapter 3.2.1 --- The Z-buffer Algorithm for HLHSR --- p.28Chapter 3.2.2 --- Our Hardware Solution for HLHSR --- p.29Chapter 3.2.3 --- Design of the Depth Processor --- p.31Chapter 3.2.4 --- Structure of the Depth Processor --- p.34Chapter 3.2.5 --- The Depth Processor Operations --- p.35Chapter 3.2.6 --- Software Support --- p.40Chapter 3.2.7 --- Performance of the Depth Processor --- p.44Chapter 3.3 --- A VGA Accelerator for the ISA Computers --- p.45Chapter 3.3.1 --- Display Buffer Structure of the SuperVGA --- p.46Chapter 3.3.2 --- Design of the VGA Accelerator --- p.47Chapter 3.3.3 --- Structure of the VGA Accelerator --- p.49Chapter 3.3.4 --- Combining the VGA Accelerator and the Depth Processor --- p.51Chapter 3.3.5 --- Actual Performance of the DP-VA Board --- p.54Chapter 3.3.6 --- 3D Graphics Applications Using the DP-VA Board --- p.55Chapter 3.4 --- A 3D Graphics Display Server --- p.57Chapter 3.5 --- Host Connection for the 3D Graphics Display Server --- p.59Chapter 3.5.1 --- The Single Board Computers --- p.60Chapter 3.5.2 --- The VME-to-ISA bus convenor --- p.61Chapter 3.5.3 --- Structure of the VME-to-ISA Bus Convertor --- p.61Chapter 3.5.4 --- Communications through the bus convertor --- p.64Chapter 3.6 --- Physical Construction of the DP-VA Board and the Bus Convertor --- p.65Chapter 3.7 --- Summary --- p.66Chapter CHAPTER 4 --- A MULTI-i860 3D GRAPHICS SYSTEMChapter 4.1 --- The i860 Processor --- p.69Chapter 4.2 --- Design of a Multiprocessor 3D Graphics System --- p.70Chapter 4.2.1 --- A Reconfigurable Processor-Pipeline System --- p.72Chapter 4.2.2 --- The Depth-Processing Unit --- p.73Chapter 4.2.3 --- A Multiprocessor Graphics System --- p.75Chapter 4.3 --- Structure of the Multi-i860 3D --- p.77Chapter 4.3.1 --- The 64-bit-wide Global Data Buses --- p.77Chapter 4.3.2 --- The 1280x1024 True-colour Display Unit --- p.79Chapter 4.3.3 --- The Depth Processing Unit --- p.82Chapter 4.3.4 --- The i860 Processing Units --- p.84Chapter 4.3.5 --- The System Control Unit --- p.87Chapter 4.3.6 --- Performance Prediction --- p.89Chapter 4.4 --- Summary --- p.90Chapter CHAPTER 5 --- CONCLUSIONSChapter 5.1 --- The 3D Graphics Synthesis Pipeline ……… --- p.91Chapter 5.2 --- 3D Graphics Hardware --- p.91Chapter 5.3 --- Design Approach for the ISA 3D Graphics Display Server --- p.92Chapter 5.4 --- Flexibility in the Multi-i860 3D Graphics System --- p.93Chapter 5.5 --- Future Work --- p.94Chapter APPENDIX A --- DISPLAYING REALISTIC 3D SCENESChapter A.1 --- Modelling 3D Objects in Boundary Representation --- p.96Chapter A.2 --- Transformations of 3D scenes --- p.98Chapter A.2.1 --- Composite Modelling Transformation --- p.98Chapter A.2.2 --- Viewing Transformations --- p.99Chapter A.2.3 --- Projection --- p.102Chapter A.2.4 --- Window to Viewport Mapping --- p.104Chapter A.3 --- Implementation of the Viewing Pipeline --- p.105Chapter A.3.1 --- Defining the View Volume --- p.105Chapter A.3.2 --- Normalization of The View Volume --- p.106Chapter A.3.3 --- The Overall Transformation Pipeline --- p.108Chapter A.4 --- Rendering Realistic 3D Scenes --- p.108Chapter A.4.1 --- Scan-conversion of Lines and Polygons --- p.108Chapter A.4.2 --- Hidden Surface Removal --- p.109Chapter A.4.3 --- Shading --- p.112Chapter A.4.4 --- The Complete 3D Graphics Pipeline --- p.114Chapter APPENDIX B --- DEPTH PROCESSOR DESIGN DETAILSChapter B.l --- PAL Definitions --- p.116Chapter B.2 --- Circuit Diagrams --- p.118Chapter B.3 --- Depth Processor User's Guide --- p.121Chapter APPENDIX C --- VGA ACCELERATOR DESIGN DETAILSChapter C.1 --- PAL Definitions --- p.124Chapter C.2 --- Circuit Diagram --- p.125Chapter C.3 --- The DP-VA User's Guide --- p.127Chapter APPENDIX D --- VME-TO-ISA BUS CONVERTOR DESIGN DETAILSChapter D.1 --- PAL Definitions --- p.131Chapter D.2 --- Circuit Diagrams --- p.133Chapter APPENDIX E --- 3D GRAPHICS LIBRARY ROUTINES FOR THE DP-VA BOARDChapter E.1 --- 3D Drawing Routines --- p.136Chapter E.2 --- 3D Transformation Routines --- p.137Chapter E.3 --- Shading Routines --- p.138Chapter APPENDIX F --- PIPELINE CONFIGURATIONS FOR N PROCESSORSREFERENCE