A New Multi-core CPU Resource Availability Prediction Model for Concurrent Processes

The efficiency of a multi-core architecture is directly related to the mechanisms that map the threads (processes in execution) to the cores. Determining the CPU resource availability of a multi-core architecture based on the characteristics of the threads that are in execution is the art of system performance prediction. Prediction of CPU resource availability is important in the context of making process assignment, load balancing, and scheduling decisions. In distributed infrastructure, CPU resources are allocated on demand for a chosen set of compute nodes. In this paper, a prediction model is derived for multi-core architectures and empirical evaluations are performed with real-world benchmark programs in a heterogeneous environment to demonstrate the accuracy of the proposed model. This model can be utilized in various time-sensitive applications like resource allocation in a cloud environment, task distribution (determining the order for faster processing time) in distributed systems, and others.Ye

A Graph-Partition-Based Scheduling Policy for Heterogeneous Architectures

In order to improve system performance efficiently, a number of systems choose to equip multi-core and many-core processors (such as GPUs). Due to their discrete memory these heterogeneous architectures comprise a distributed system within a computer. A data-flow programming model is attractive in this setting for its ease of expressing concurrency. Programmers only need to define task dependencies without considering how to schedule them on the hardware. However, mapping the resulting task graph onto hardware efficiently remains a challenge. In this paper, we propose a graph-partition scheduling policy for mapping data-flow workloads to heterogeneous hardware. According to our experiments, our graph-partition-based scheduling achieves comparable performance to conventional queue-base approaches.Comment: Presented at DATE Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems (HIS 2015) (arXiv:1502.07241