Underwater acoustic communications and adaptive signal processing

This dissertation proposes three new algorithms for underwater acoustic wireless communications. One is a new tail-biting circular MAP decoder for full tail-biting convolution (FTBC) codes for very short data blocks intended for Internet of Underwater Things (IoUT). The proposed algorithm was evaluated by ocean experiments and computer simulations on both Physical (PHY) and Media access control (MAC) layers. The ocean experimental results show that without channel equalization, the full tail-biting convolution (FTBC) codes with short packet lengths not only can perform similarly to zero-tailing convolution (ZTC) codes in terms of bit error rate (BER) in the PHY layer. Computer simulation results show that the FTBC codes outperform the ZTC codes in terms of MAC layer metrics, such as collision rate and bandwidth utilization, in a massive network of battery powered IoUT devices. Second, this dissertation also proposes a new approach to utilizing the underwater acoustic (UWA) wireless communication signals acquired in a real-world experiment as a tool for evaluating new coding and modulation schemes in realistic doubly spread UWA channels. This new approach, called passband data reuse, provides detailed procedures for testing the signals under test (SUT) that change or add error correction coding, change bit to symbol mapping (baseband modulation) schemes from a set of original experimental data --Abstract, page iv

CMOS analog map decoder for (8,4) hamming code

Journal ArticleAbstract-Design and test results for a fully integrated translinear tail-biting MAP error-control decoder are presented. Decoder designs have been reported for various applications which make use of analog computation, mostly for Viterbi-style decoders. MAP decoders are more complex, and are necessary components of powerful iterative decoding systems such as Turbo codes. Analog circuits may require less area and power than digital implementations in high-speed iterative applications. Our (8, 4) Hamming decoder, implemented in an AMI 0.5- m process, is the first functioning CMOS analog MAP decoder. While designed to operate in subthreshold, the decoder also functions above threshold with a small performance penalty. The chip has been tested at bit rates up to 2 Mb/s, and simulations indicate a top speed of about 10 Mb/s in strong inversion. The decoder circuit size is 0.82 mm2, and typical power consumption is 1 mW at 1 Mb/s

Improving the tolerance of stochastic LDPC decoders to overclocking-induced timing errors: a tutorial and design example

Channel codes such as Low-Density Parity-Check (LDPC) codes may be employed in wireless communication schemes for correcting transmission errors. This tolerance to channel-induced transmission errors allows the communication schemes to achieve higher transmission throughputs, at the cost of requiring additional processing for performing LDPC decoding. However, this LDPC decoding operation is associated with a potentially inadequate processing throughput, which may constrain the attainable transmission throughput. In order to increase the processing throughput, the clock period may be reduced, albeit this is at the cost of potentially introducing timing errors. Previous research efforts have considered a paucity of solutions for mitigating the occurrence of timing errors in channel decoders, by employing additional circuitry for detecting and correcting these overclocking-induced timing errors. Against this background, in this paper we demonstrate that stochastic LDPC decoders (LDPC-SDs) are capable of exploiting their inherent error correction capability for correcting not only transmission errors, but also timing errors, even without the requirement for additional circuitry. Motivated by this, we provide the first comprehensive tutorial on LDPC-SDs. We also propose a novel design flow for timing-error-tolerant LDPC decoders. We use this to develop a timing error model for LDPC-SDs and investigate how their overall error correction performance is affected by overclocking. Drawing upon our findings, we propose a modified LDPC-SD, having an improved timing error tolerance. In a particular practical scenario, this modification eliminates the approximately 1 dB performance degradation that is suffered by an overclocked LDPC-SD without our modification, enabling the processing throughput to be increased by up to 69.4%, which is achieved without compromising the error correction capability or processing energy consumption of the LDPC-SD