2 research outputs found
Application-level Studies of Cellular Neural Network-based Hardware Accelerators
As cost and performance benefits associated with Moore's Law scaling slow,
researchers are studying alternative architectures (e.g., based on analog
and/or spiking circuits) and/or computational models (e.g., convolutional and
recurrent neural networks) to perform application-level tasks faster, more
energy efficiently, and/or more accurately. We investigate cellular neural
network (CeNN)-based co-processors at the application-level for these metrics.
While it is well-known that CeNNs can be well-suited for spatio-temporal
information processing, few (if any) studies have quantified the
energy/delay/accuracy of a CeNN-friendly algorithm and compared the CeNN-based
approach to the best von Neumann algorithm at the application level. We present
an evaluation framework for such studies. As a case study, a CeNN-friendly
target-tracking algorithm was developed and mapped to an array architecture
developed in conjunction with the algorithm. We compare the energy, delay, and
accuracy of our architecture/algorithm (assuming all overheads) to the most
accurate von Neumann algorithm (Struck). Von Neumann CPU data is measured on an
Intel i5 chip. The CeNN approach is capable of matching the accuracy of Struck,
and can offer approximately 1000x improvements in energy-delay product
Efficient Analog Circuits for Boolean Satisfiability
Efficient solutions to NP-complete problems would significantly benefit both
science and industry. However, such problems are intractable on digital
computers based on the von Neumann architecture, thus creating the need for
alternative solutions to tackle such problems. Recently, a deterministic,
continuous-time dynamical system (CTDS) was proposed (Nat.Phys. {\bf 7}(12),
966 (2011)) to solve a representative NP-complete problem, Boolean
Satisfiability (SAT). This solver shows polynomial analog time-complexity on
even the hardest benchmark -SAT () formulas, but at an energy cost
through exponentially driven auxiliary variables. This paper presents a novel
analog hardware SAT solver, AC-SAT, implementing the CTDS via incorporating
novel, analog circuit design ideas. AC-SAT is intended to be used as a
co-processor and is programmable for handling different problem specifications.
It is especially effective for solving hard -SAT problem instances that are
challenging for algorithms running on digital machines. Furthermore, with its
modular design, AC-SAT can readily be extended to solve larger size problems,
while the size of the circuit grows linearly with the product of the number of
variables and number of clauses. The circuit is designed and simulated based on
a 32nm CMOS technology. SPICE simulation results show speedup factors of
10 on even the hardest 3-SAT problems, when compared with a
state-of-the-art SAT solver on digital computers. As an example, for hard
problems with variables and clauses, solutions are found within
from a few to a few hundred .Comment: 9 pages, 9 Figures, 1 Table. Added journal info in version 2: IEEE
Transactions on Very Large Scale Integration Systems (TVLSI) vol 26, No 1,
January 2018, pp 155-167. DOI: 10.1109/TVLSI.2017.275419