4,131 research outputs found
Polynomial-time T-depth Optimization of Clifford+T circuits via Matroid Partitioning
Most work in quantum circuit optimization has been performed in isolation
from the results of quantum fault-tolerance. Here we present a polynomial-time
algorithm for optimizing quantum circuits that takes the actual implementation
of fault-tolerant logical gates into consideration. Our algorithm
re-synthesizes quantum circuits composed of Clifford group and T gates, the
latter being typically the most costly gate in fault-tolerant models, e.g.,
those based on the Steane or surface codes, with the purpose of minimizing both
T-count and T-depth. A major feature of the algorithm is the ability to
re-synthesize circuits with additional ancillae to reduce T-depth at
effectively no cost. The tested benchmarks show up to 65.7% reduction in
T-count and up to 87.6% reduction in T-depth without ancillae, or 99.7%
reduction in T-depth using ancillae.Comment: Version 2 contains substantial improvements and extensions to the
previous version. We describe a new, more robust algorithm and achieve
significantly improved experimental result
Error suppression via complementary gauge choices in Reed-Muller codes
Concatenation of two quantum error correcting codes with complementary sets
of transversal gates can provide a means towards universal fault-tolerant
computation. We first show that it is generally preferable to choose the inner
code with the higher pseudo-threshold in order to achieve lower logical failure
rates. We then explore the threshold properties of a wide range of
concatenation schemes. Notably, we demonstrate that the concatenation of
complementary sets of Reed-Muller codes can increase the code capacity
threshold under depolarizing noise when compared to extensions of previously
proposed concatenation models. We also analyze the properties of logical errors
under circuit level noise, showing that smaller codes perform better for all
sampled physical error rates. Our work provides new insights into the
performance of universal concatenated quantum codes for both code capacity and
circuit level noise.Comment: 11 pages + 4 appendices, 6 figures. In v2, Fig.1 was added to conform
to journal specification
Estimating the cost of generic quantum pre-image attacks on SHA-2 and SHA-3
We investigate the cost of Grover's quantum search algorithm when used in the
context of pre-image attacks on the SHA-2 and SHA-3 families of hash functions.
Our cost model assumes that the attack is run on a surface code based
fault-tolerant quantum computer. Our estimates rely on a time-area metric that
costs the number of logical qubits times the depth of the circuit in units of
surface code cycles. As a surface code cycle involves a significant classical
processing stage, our cost estimates allow for crude, but direct, comparisons
of classical and quantum algorithms.
We exhibit a circuit for a pre-image attack on SHA-256 that is approximately
surface code cycles deep and requires approximately
logical qubits. This yields an overall cost of
logical-qubit-cycles. Likewise we exhibit a SHA3-256 circuit that is
approximately surface code cycles deep and requires approximately
logical qubits for a total cost of, again,
logical-qubit-cycles. Both attacks require on the order of queries in
a quantum black-box model, hence our results suggest that executing these
attacks may be as much as billion times more expensive than one would
expect from the simple query analysis.Comment: Same as the published version to appear in the Selected Areas of
Cryptography (SAC) 2016. Comments are welcome
Magic-State Functional Units: Mapping and Scheduling Multi-Level Distillation Circuits for Fault-Tolerant Quantum Architectures
Quantum computers have recently made great strides and are on a long-term
path towards useful fault-tolerant computation. A dominant overhead in
fault-tolerant quantum computation is the production of high-fidelity encoded
qubits, called magic states, which enable reliable error-corrected computation.
We present the first detailed designs of hardware functional units that
implement space-time optimized magic-state factories for surface code
error-corrected machines. Interactions among distant qubits require surface
code braids (physical pathways on chip) which must be routed. Magic-state
factories are circuits comprised of a complex set of braids that is more
difficult to route than quantum circuits considered in previous work [1]. This
paper explores the impact of scheduling techniques, such as gate reordering and
qubit renaming, and we propose two novel mapping techniques: braid repulsion
and dipole moment braid rotation. We combine these techniques with graph
partitioning and community detection algorithms, and further introduce a
stitching algorithm for mapping subgraphs onto a physical machine. Our results
show a factor of 5.64 reduction in space-time volume compared to the best-known
previous designs for magic-state factories.Comment: 13 pages, 10 figure
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