Neuromorphic electronics for real-time biomedical image processing

Published versio

The Telecommunications and Data Acquisition Report

This publication, one of a series formerly titled The Deep Space Network Progress Report, documents DSN progress in flight project support, tracking and data acquisition research and technology, network engineering, hardware and software implementation, and operations. In addition, developments in Earth-based radio technology as applied to geodynamics, astrophysics and the radio search for extraterrestrial intelligence are reported

Workshop on Fuzzy Control Systems and Space Station Applications

The Workshop on Fuzzy Control Systems and Space Station Applications was held on 14-15 Nov. 1990. The workshop was co-sponsored by McDonnell Douglas Space Systems Company and NASA Ames Research Center. Proceedings of the workshop are presented

The Multispectral Imaging Science Working Group. Volume 3: Appendices

The status and technology requirements for using multispectral sensor imagery in geographic, hydrologic, and geologic applications are examined. Critical issues in image and information science are identified

Parallel Algorithms for Isolated and Connected Word Recognition

For years researchers have worked toward finding a way to allow people to talk to machines in the same manner a person communicates to another person. This verbal man to machine interface, called speech recognition, can be grouped into three types: isolated word recognition, connected word recognition, and continuous speech recognition. Isolated word recognizers recognize single words with distinctive pauses before and after them. Continuous speech recognizers recognize speech spoken as one person speaks to another, continuously without pauses. Connected word recognition is an extension of isolated word recognition which recognizes groups of words spoken continuously. A group of words must have distinctive pauses before and after it, and the number of words in a group is limited to some small value (typically less than six). If these types of recognition systems are to be successful in the real world, they must be speaker independent and support a large vocabulary. They also must be able to recognize the speech input accurately and in real time. Currently there is no system which can meet all of these criteria because a vast amount of computations are needed. This report examines the use of parallel processing to reduce the computation time for speech recognition. Two different types of parallel architectures are considered here, the Single Instruction stream - Multiple Data (S1MD) machine and the VLSI processor array. The SIMD machine is chosen for its flexibility, which makes it a good candidate for testing new speech recognition algorithms. The VLSI processor array is selected as being good for a dedicated recognition system because of its simple processors and fixed interconnections. This report involves designing SIMD systems and VLSI processor arrays for both isolated and connected word recognition systems. These architectures are evaluated and contrasted in terms of the number of processors needed, the interprocessor connections required, and the “power” each processor needs to achieve real time recognition. The results show that an SIMD machine using 100 processors, each with an MC68000 processor, can recognize isolated words in real time using a 20 KHz sampling rate and a 1,000 word vocabulary

Efficient Macromodeling and Fast Transient Simulation of High Speed Distributed Interconnects

In the first part of the thesis, an efficient macromodeling technique based on Loewner Matrix (LM) approach has been presented to model multi-port distributed systems using tabulated noisy data. In the proposed method, Loewner Model data from previous rational approximation are used to create less noisy eigenvectors in an iterative manner. As a result, the biasing effect of the LM model approximated by the noisy data is reduced. It is illustrated that this method improves the accuracy of the Loewner Matrix modeling for noisy frequency data. In the second part, a fast and robust algorithm is introduced for time-domain simulation of interconnects with few nonlinear elements based on Large Change Sensitivity approach. After macromodeling interconnects, linear parts of the system construct very large matrix. Large linear matrix with nonlinear components makes time domain simulation a Central Processing Unit (CPU) intensive task where inversion (one Lower/Upper (LU) decomposition and one forward/backward substitution) of this large matrix is done at each step of the Newton-Raphson iteration. Using the proposed method, large system matrix is partitioned into linear and nonlinear parts and LU decomposition of linear matrix is done only once in the entire simulation. Nonlinear elements construct a very small matrix compared to large linear matrix. In this proposed method, small matrix is inverted at each Newton iteration. Cost of inverting a small matrix is much cheaper than inverting a very large matrix. Therefore, this approach is faster than the conventional matrix inversion method. Numerical examples are presented illustrating validity and efficiency of the above method

IP protection for DSP algorithms\u27 FPGA implementation.

With today\u27s system-on-chip (SOC) technology, we are able to design larger and more complicated application-specific integrated circuits (ASICs) and field programmable gate array (FPGA) in shorter time period. The key point of the success of SOC technology is the reuse of intellectual property (IP) cores. Consequently the copyright protection for these IP cores becomes the major concern for the development pace of SOC technology. Watermarking technology has been proved to be an effective way of copyright protection. In this thesis, the author presents two new watermarking algorithms respectively at algorithm level and FPGA layout level. The simulations and implementation results show that the new proposals have much less design and hardware implementation overheads, lower watermark embedding and extraction cost, as well as higher security strength, compared to the previously proposed methods.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis2004 .D39. Source: Masters Abstracts International, Volume: 43-03, page: 0929. Advisers: H. K. Kwan; H. Wu. Thesis (M.A.Sc.)--University of Windsor (Canada), 2004

Data Visualization for Benchmarking Neural Networks in Different Hardware Platforms

The computational complexity of Convolutional Neural Networks has increased enor mously; hence numerous algorithmic optimization techniques have been widely proposed. However, in a space design so complex, it is challenging to choose which optimization will benefit from which type of hardware platform. This is why QuTiBench - a benchmarking methodology - was recently proposed, and it provides clarity into the design space. With measurements resulting in more than nine thousand data points, it became difficult to get useful and rich information quickly and intuitively from the vast data collected. Thereby this effort describes the creation of a web portal where all data is exposed and can be adequately visualized. All the code developed in this project resides in an online public GitHub repository, allowing contributions. Using visualizations which grab our interest and keep our eyes on the message is the perfect way to understand the data and spot trends. Thus, several types of plots were used: rooflines, heatmaps, line plots, bar plots and Box and Whisker Plots. Furthermore, as level-0 of QuTiBench performs a theoretical analysis of the data, with no measurements required, performance predictions were evaluated. We concluded that predictions successfully predicted performance trends. Although being somewhat optimistic because predictions become inaccurate with the increased pruning and quan tization. The theoretical analysis could be improved by the increased awareness of what data is stored in the on and off-chip memory. Moreover, for the FPGAs, performance predictions can be further enhanced by taking the actual resource utilization and the achieved clock frequency of the FPGA circuit into account. With these improvements to level-0 of QuTiBench, this benchmarking methodology can become more accurate on the next measurements, becoming more reliable and useful to designers. Moreover, more measurements were taken, in particular, power, performance and accuracy measurements were taken for Google’s USB Accelerator benchmarking Efficient Net S, EfficientNet M and EfficientNet L. In general, performance measurements were reproduced; however, it was not possible to reproduce accuracy measurements

Miniaturized Transistors, Volume II

In this book, we aim to address the ever-advancing progress in microelectronic device scaling. Complementary Metal-Oxide-Semiconductor (CMOS) devices continue to endure miniaturization, irrespective of the seeming physical limitations, helped by advancing fabrication techniques. We observe that miniaturization does not always refer to the latest technology node for digital transistors. Rather, by applying novel materials and device geometries, a significant reduction in the size of microelectronic devices for a broad set of applications can be achieved. The achievements made in the scaling of devices for applications beyond digital logic (e.g., high power, optoelectronics, and sensors) are taking the forefront in microelectronic miniaturization. Furthermore, all these achievements are assisted by improvements in the simulation and modeling of the involved materials and device structures. In particular, process and device technology computer-aided design (TCAD) has become indispensable in the design cycle of novel devices and technologies. It is our sincere hope that the results provided in this Special Issue prove useful to scientists and engineers who find themselves at the forefront of this rapidly evolving and broadening field. Now, more than ever, it is essential to look for solutions to find the next disrupting technologies which will allow for transistor miniaturization well beyond silicon’s physical limits and the current state-of-the-art. This requires a broad attack, including studies of novel and innovative designs as well as emerging materials which are becoming more application-specific than ever before