A reconfigurable 60GHz receiver : providing robustness to process variations

The problems associated with process-induced variability and other challenges of 60GHz circuit design and measurement are treated in this thesis. A system-level analysis is performed on a generic RF receiver. For doing that, first, bit error rate (BER) is considered as a figure of merit representing the overall performance of the Receiver. Then, each stage of the receiver is described by three parameters: voltage gain, noise, and nonlinearity which are prone to variation due to process spread. The variation of these parameters represents all lower-level sources of variability. Since bit error rate (BER), as a major performance measure of the receiver, is a direct function of the noise and distortion, the contribution of each block to the overall noise plus distortion (NPD) is analyzed, which opens the way for minimization of the sensitivity of the NPD to the performance variation of individual stages. It is shown that the first order sensitivities of NPD to the individual gains of the building blocks can all be made zero. Its second order sensitivity to the gains of the building blocks can be reduced. Its sensitivity to noise and nonlinearity of an individual building block can be reduced, but at the cost of that of other blocks; its sensitivity to noise and nonlinearity cannot be reduced over the whole system. Three design approaches are proposed, analyzed and compared. Statistical and corner simulations are performed to confirm the validity of the proposed guidelines showing significant improvement in the yield of the designs. Applying the analysis to a zero-IF three-stage 60 GHz receiver shows a significant improvement in the design yield, by nullifying the first order sensitivities of the overall performance to the individual gains of the blocks. Reduction of the second order sensitivity of the NPD to the gain of individual stages, by keeping the contribution factor of all the stages below one, results in further improvements in the design yield. The conventional optimum-power design methodology has been modified in a way that it nullifies the first order sensitivities of NPD to the individual gains of all the stages. It is shown that for simultaneous power optimization and reduced second-order sensitivity to the gains of the blocks less power hungry building blocks must be in the rear stages of the receiver and more power hungry ones in the front. After identifying the limitations of a pure system-level approach, i.e., inability to suppress the sensitivity of the overall performance to the noise and nonlinearity of all the blocks, the focus is shifted towards circuit-level methods by providing re-configurability to some RF circuits. A receiver is designed with good noise and nonlinearity performance and with accumulated noise and nonlinearity distortion contribution in its last stage (mixer). As a result, the overall performance of the receiver is more sensitive to the performance variations of the mixer. Simulations show that it is possible to correct the overall receiver performance degradations resulting from process variations by just tuning the performance of the mixer. Furthermore, a tunable mixer is presented for minimizing the IMD2 across a wide IF bandwidth. It is demonstrated both in theory and measurement that a presented three-dimensional tuning method is beneficial for wideband cancellation of second order intermodulation distortions (IMD2) in a zero-IF downconverter. A 60GHz zero-IF mixer is designed and measured on-wafer to show that the proposed tuning mechanism can simultaneously suppress IMD2 tones across the whole 1GHz IF band. To address the challenges of 60GHz circuit design, a design methodology is utilized which serves to properly model the parasitic effects and improve the predictability of the performance. The parasitic effects due to layout, which are more influential at high frequencies, are taken into account by performing automatic RC extraction and manual L extraction. The long signal lines are modeled with distributed RLC networks. The problem of substrate losses is addressed by using patterned ground shields in inductors and transmission lines. The cross-talk issue is treated by using distributed meshed ground lines, decoupled DC lines, and grounded substrate contacts around sensitive RF components. However, in practice, it is observed that accurate simulation of all the effects is sometimes very time consuming or even infeasible. For instance electromagnetic simulation of a transformer in the presence of all the dummy metals is beyond the computational capability of existing EM-simulators. Three 60GHz receiver components are analyzed, designed, and measured with good performance. A two-stage fully integrated 60 GHz differential low noise amplifier is implemented in a CMOS 65 nm bulk technology with superior noise figure compared to state-of-the-art mm-wave LNAs. A doublebalanced 60 GHz mixer with ac-coupled RF input is designed and measured with a series capacitor in the input RF path to suppress the low frequency second order intermodulation distortions generated in the previous stage. A quadrature 60 GHz VCO is presented which exhibits a comparable level of performance, in particular very good phase noise, to state-of-the-art single-phase VCOs, despite the additional challenges and limitations imposed by the quadrature topology. The on-wafer measurements on the 60GHz circuits designed in this work are performed using a waveguide-based measurement setup. The fixed waveguide structures, specially provided for the probe station, serve for the robustness of the setup as they circumvent the need for cables, which are by nature difficult to rigidify, in the vicinity of the probes. Taking advantage of magic- Ts, it is possible to measure differential mm-wave circuits with a two-port network analyzer rather than using a much more expensive four-port one. Noise, s-parameter, and phase noise measurements are performed using the mentioned setups

System level receiver design for minimum sensitivity to process variations

A system-level design methodology is proposed to reduce the sensitivity of an integrated zero-IF receiver, including the analog-to-digital converter, to performance variations of its components due to process spreading. Describing each stage of the receiver by three parameters of voltage gain, noise, and nonlinearity, whose variations represent all lower-level sources of variability, the sensitivity of the overall performance to the variations of these parameters is calculated. Three design approaches are proposed, analyzed, and compared for reducing these sensitivities. Statistical and corner simulations are performed to con¿rm the validity of the proposed guidelines showing signi¿cant improvement in the yield of the designs