9 research outputs found

    An efficient graph representation for arithmetic circuit verification

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    Improving BDD Based Symbolic Model Checking with Isomorphism Exploiting Transition Relations

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    Symbolic model checking by using BDDs has greatly improved the applicability of model checking. Nevertheless, BDD based symbolic model checking can still be very memory and time consuming. One main reason is the complex transition relation of systems. Sometimes, it is even not possible to generate the transition relation, due to its exhaustive memory requirements. To diminish this problem, the use of partitioned transition relations has been proposed. However, there are still systems which can not be verified at all. Furthermore, if the granularity of the partitions is too fine, the time required for verification may increase. In this paper we target the symbolic verification of asynchronous concurrent systems. For such systems we present an approach which uses similarities in the transition relation to get further memory reductions and runtime improvements. By applying our approach, even the verification of systems with an previously intractable transition relation becomes feasible.Comment: In Proceedings GandALF 2011, arXiv:1106.081

    Formal verification of an ARM processor

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    Mapping switch-level simulation onto gate-level hardware accelerators

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    In this paper, we present a framework for performing switch-level simulation on hardware accelerators

    *PHDD: an efficient graph representation for floating point circuit verification

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    A Methodology for Hardware Verification Based on Logic Simulation.

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    Symbolic Representation with Ordered Function Templates

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    Binary Decision Diagrams (BDDs) often fail to exploit sharing between Boolean functions that differ only in their support variables. In a memory circuit, for example, the functions for the different bits of a word differ only in the data bit while the address decoding part of the function is identical. We present a symbolic representation approach using ordered function templates to exploit such regularity. Templates specify functionality without being bound to a specific set of variables. Functions are obtained by instantiating templates with a list of variables. We ensure canonicity of the representation by requiring that templates are normalized and argument lists are ordered. We also present algorithms for performing Boolean operations using this representation. Experiments with a prototype implementation built on top of CUDD indicate that function templates can dramatically reduce memory requirements for symbolic simulation of regular circuits

    Symbolic Representation with Ordered Function Templates

    No full text
    Binary Decision Diagrams (BDDs) often fail to exploit sharing between Boolean functions that differ only in their support variables. In a memory circuit, for example, the functions for the different bits of a word differ only in the data bit while the address decoding part of the function is identical. We present a symbolic representation approach using ordered function templates to exploit such regularity. Templates specif
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