Superpipelined reconfigurable hardware for DSP

Abstract- Reconfigurable hardware offers a number of ad- embedded FPGA [5]. The MONTIUM architecture integrates vantages over custom integrated circuits, including low devel- a microprocessor with an FPGA and an array of coarseopment cost, high flexibility, and high adaptability to changing grain cells, each containing several 16-bit ALUs [6]. These requirements. However, this alternative does incur some reduction in performance, especially for computationally intensive coarse-gran archlitectures achieve higher performance, but tasks such as digital signal processing. Recent developments their functionality typically is limited to a set of basic functions in both research and industry have aimed to reduce this gap. such as multiplication and addition. This paper introduces a novel reconfigurable architecture that Another way to improve the performance of reconfigurable pipelines computations at the bit level. The architecture includes hardware is to pipeline the datapath. This approach works a number offeatures to improve performance, includingmediumgrain cells, hierarchical interconnections, and minimal clocking well for DSP, since many algorithms apply a series of stanoverhead. Circuit simulations demonstrate that the basic cell runs dard operations across a large data set. However, traditional at 1.5 GHz in a modest 180-nm technology. At this speed, we reconfigurable devices only support pipelining to a limited estimate that the device could compute a 256-point Fast Fourier extent. The interconnection network typically does not pipeline Transform in 829 ns. I