Ultra-Low-Power Superconductor Logic

We have developed a new superconducting digital technology, Reciprocal Quantum Logic, that uses AC power carried on a transmission line, which also serves as a clock. Using simple experiments we have demonstrated zero static power dissipation, thermally limited dynamic power dissipation, high clock stability, high operating margins and low BER. These features indicate that the technology is scalable to far more complex circuits at a significant level of integration. On the system level, Reciprocal Quantum Logic combines the high speed and low-power signal levels of Single-Flux- Quantum signals with the design methodology of CMOS, including low static power dissipation, low latency combinational logic, and efficient device count.Comment: 7 pages, 5 figure

Atomically Thin Al2 O3 Films for Tunnel Junctions

Metal-insulator-metal tunnel junctions are common throughout the microelectronics industry. The industry standard AlOx tunnel barrier, formed through oxygen diffusion into an Al wetting layer, is plagued by internal defects and pinholes which prevent the realization of atomically thin barriers demanded for enhanced quantum coherence. In this work, we employ in situ scanning tunneling spectroscopy along with molecular-dynamics simulations to understand and control the growth of atomically thin Al2O3 tunnel barriers using atomic-layer deposition. We find that a carefully tuned initial H2O pulse hydroxylated the Al surface and enabled the creation of an atomically thin Al2O3 tunnel barrier with a high-quality M-I interface and a significantly enhanced barrier height compared to thermal AlOx. These properties, corroborated by fabricated Josephson junctions, show that atomic-layer deposition Al2O3 is a dense, leak-free tunnel barrier with a low defect density which can be a key component for the next generation of metal-insulator-metal tunnel junctions

Defect-based testing of LTS digital circuits

A Defect-Based Test (DBT) methodology for Superconductor Electronics (SCE) is presented in this thesis, so that commercial production and efficient testing of systems can be implemented in this technology in the future. In the first chapter, the features and prospects for SCE have been presented. The motivation for this research and the outline of the thesis were also described in Chapter 1. It has been shown that high-end applications such as Software-Defined Radio (SDR) and petaflop computers which are extremely difficult to implement in top-of-the-art semiconductor technologies can be realised using SCE. But, a systematic structural test methodology had yet to be developed for SCE and has been addressed in this thesis. A detailed introduction to Rapid Single-Flux Quantum (RSFQ) circuits was presented in Chapter 2. A Josephson Junction (JJ) was described with associated theory behind its operation. The JJ model used in the simulator used in this research work was also presented. RSFQ logic with logic protocols as well as the design and implementation of an example D-type flip-flop (DFF) was also introduced. Finally, advantages and disadvantages of RSFQ circuits have been discussed with focus on the latest developments in the field. Various techniques for testing RSFQ circuits were discussed in Chapter 3. A Process Defect Monitor (PDM) approach was presented for fabrication process analysis. The presented defect-monitor structures were used to gather measurement data, to find the probability of the occurrence of defects in the process which forms the first step for Inductive Fault Analysis (IFA). Results from measurements on these structures were used to create a database for defects. This information can be used as input for performing IFA. "Defect-sprinkling" over a fault-free circuit can be carried out according to the measured defect densities over various layers. After layout extraction and extensive fault simulation, the resulting information will indicate realistic faults. In addition, possible Design-for-Testability (DfT) schemes for monitoring Single-Flux Quantum (SFQ) pulses within an RSFQ circuit has also been discussed in Chapter 3. The requirement for a DfT scheme is inevitable for RSFQ circuits because of their very high frequency of operation and very low operating temperature. It was demonstrated how SFQ pulses can be monitored at an internal node of an SCE circuit, introducing observability using Test-Point Insertion (TPI). Various techniques were discussed for the introduction of DfT and to avoid the delay introduced by the DfT structure if it is required. The available features in the proposed design for customising the detector make it attractive for a detailed DBT of RSFQ circuits. The control of internal nodes has also been illustrated using TPI. The test structures that were designed and implemented to determine the occurrence of defects in the processes can also be used to locate the position for the insertion of the above mentioned DfT structures

Josephson Junctions with Tunnel Barriers Grown Via In Situ Atomic Layer Deposition

Since the 1970's, silicon technology has increased processing power by increasing the density of silicon transistors according to Moore's Law. However, silicon transistor feature sizes are approaching a minimum size limit, and a new paradigm is required to continue progress. Quantum computing is a promising paradigm that relies on the entanglement of macroscopic quantum objects, called qubits, to perform calculations. Josephson junction (JJ) based qubits are a promising candidate for the implementation of quantum computers. However, JJ qubits have suffered from poor coherence. A major source of decoherence in JJ qubits is two-level fluctuators in the insulating materials of the JJ circuit, particularly oxygen vacancies and interstitials in the thermally oxidized tunnel barrier. In order to realize the full potential of JJ qubits, an alternative method to thermal oxidation must be found for tunnel barrier growth. This work explores using atomic layer deposition (ALD) for the growth of ultrathin (~ 1 nm) tunnel barriers in JJs. A unique thin film deposition tool was built which integrates ultra-high vacuum sputtering with ALD in situ. The growth of ALD-Al2O3 on in situ sputtered Al films was studied in depth. Atomic force microscopy and ellipsometry were used to determine that ALD-Al2O3 grows conformally on Al, but a ~ 2 nm thermally oxidized interfacial layer (IL) develops between the Al and Al2O3 for ALD films > 2 nm. The thickness of this IL decreased when the Al film was 2 nm. The thickness of this IL decreased when the Al film was < 2 nm, confirming the IL is a thermal oxide. As a proof of concept, Nb/Al/ALD-Al2O3/Nb trilayers with ultrathin (< 1 nm) tunnel barriers were grown and processed into JJs. The junction specific resistance and gap current density were found to depend exponentially on the ALD film thickness, indicating that the tunnel barrier thickness can be controlled by ALD. Despite evidence for an estimated 0.8 nm interfacial layer in the ultrathin tunnel barrier, this work incontrovertibly concludes that ALD can be used to produce quality JJs

Controlling Interface for Metal-Insulator-Metal Architectures with Ultrathin Dielectric Fabricated Using Atomic Layer Deposition and Sputtering

The miniaturization of future microelectronics demands the development of high quality ultrathin (few to sub-nm) dielectric films for application in metal-insulator-metal (MIM) architectures. Among all other approaches employed for ultrathin dielectric film fabrication, atomic layer deposition (ALD) provides a unique approach for the fabrication of ultrathin TBs with several advantages including an atomic-scale control on the TB thickness, conformal coating, and low defects density. Despite extensive efforts in ALD devices, the figure-of-merit dielectric constant (r) exhibits a significant monotonic decrease with the film thickness as compared to bulk single crystal value. Primarily, the control over metal-insulator (M-I) interface, specifically in ultrathin thickness range, remains a challenge due to the formation of defective oxides and interfacial layer (IL). This work demonstrates the development of high quality Al/ALD Al2O3/Al MIM trilayers using a unique in-house integrated in situ deposition (sputtering/ALD) method. These trilayers devices were characterization to understand and control the IL formation with atomic precision. To the best of our knowledge, high r ~8.9 that is within 3% of the bulk value ~9.2 has been achieved for the first time on the ALD Al2O3 films in thickness range ~3.3-4.4 nm. This corresponds to an effective oxide thickness ~1.4-1.9 nm comparable to High-K HfO2 of 3-4 nm. The low leakage current density (J) ~10-9 A/cm2 is an order of magnitude lower than the best previously reported values. These results suggest that the optimal ultrathin high quality ALD Al2O3 provides a much lower-cost alternative for gate dielectric. Also, ALD Al2O3 seed layer (SL) approach was used to illustrate the critical importance of control over M-I interface to obtain dense hydroxylation and reduce incubation period, improving the dielectric properties of ultrathin ALD MgO films. ALD MgO with SL demonstrated r ~8.8-9.4 in thickness range ~3.8-4.9 nm comparable to bulk MgO ~9.4. In contrast, low r ~3.6-4.7 was observed for ALD MgO without Al2O3 SL in a similar thickness range. Both the scanning tunnelling spectroscopy and ab-initio molecular dynamics studies point out that SL allows the initial dense nucleation and perfect interface resulting in a high quality dielectric with tunnel barrier height (Eb)~1.5 eV compared to 0.8 eV for MgO without SL. This result provides an approach to engineering incompatible M-I interface using a SL for obtaining high quality dielectric as required for applications in MIM tunnel junctions and CMOS. In addition, tuning thickness of Al wetting layer (t_Al) in capacitors consisting of Nb (25 nm)/Fe (20 nm)/ALD Al2O3 (2.2 nm)/ t_Al/Fe (20 nm)/Nb (50 nm) shows switching between pure dielectric behavior for t_Al >1 nm and ferroelectric/dielectric (FE/DE) bilayer at t_Al≤ 1 nm. These FE/DE bilayer gate with ultrathin DE are promising for low power microelectronic devices. This helps to realize FE/DE bilayer capacitors with a total FE/DE total thickness 1 nm and ferroelectric/dielectric (FE/DE) bilayer at t_Al≤ 1 nm. These FE/DE bilayer gate with ultrathin DE are promising for low power microelectronic devices. This helps to realize FE/DE bilayer capacitors with a total FE/DE total thickness < 3-4 nm that show a dynamic switching on/off of the negative capacitance under the application of an external force. This result not only provides a viable approach for generating ultrathin FE/DE bilayer capacitors but also offers a promising solution to low-power consumption microelectronics and piezoelectric sensors applications. Pinhole-free and defect-free ultrathin dielectric tunnel barriers (TBs) is a key to obtaining high tunnelling magnetoresistance (TMR) and efficient switching in magnetic tunnel junctions (MTJs). Motivated by this, this work explores fabrication and characterization of spin-valve Fe/ALD-Al2O3/Fe MTJs with ALD Al2O3 TB thickness of 0.55 nm using in situ ALD. Remarkably, high TMR values of ~77% and ~ 90% have been obtained respectively at room temperature and at 100 K, which are comparable to the best reported on MTJs having thermal AlOx TBs with optimized device structures. In situ scanning tunnelling spectroscopy characterization of the ALD Al2O3 TBs has revealed a higher tunnel barrier height Eb of 1.33 eV, in contrast to Eb~0.3-0.6 eV for their AlOx TB counterparts, indicative of significantly lower defect concentration in the former. This first success of the MTJs with sub-nm thick ALD Al2O3 TBs demonstrates the feasibility of in situ ALD for the fabrication of pinhole-free and low-defect ultrathin TBs for practical applications and the performance could be further improved through device optimization