Performance analysis and design optimization of parallel-type slew-rate enhancers for switched-capacitor applications

The design of single-stage OTAs for accurate switched-capacitor circuits involves challenging trade-offs between speed and power consumption. The addition of a Slew-Rate Enhancer (SRE) circuit placed in parallel to the main OTA (parallel-type SRE) constitutes a viable solution to reduce the settling time, at the cost of low-power overhead and no modifications of the main OTA. In this work, a practical analytical model has been developed to predict the settling time reduction achievable with OTA/SRE systems and to show the effect of the various design parameters. The model has been applied to a real case, consisting of the combination of a standard folded-cascode OTA with an existing parallel-type SRE solution. Simulations performed on a circuit designed with a commercial 180-nm CMOS technology revealed that the actual settling-time reduction was significantly smaller than predicted by the model. This discrepancy was explained by taking into account the internal delays of the SRE, which is exacerbated when a high output current gain is combined with high power efficiency. To overcome this problem, we propose a simple modification of the original SRE circuit, consisting in the addition of a single capacitor which temporarily boosts the OTA/SRE currents reducing the internal turn-on delay. With the proposed approach a settling-time reduction of 57% has been demonstrated with an SRE that introduces only a 10% power-overhead with respect of the single OTA solution. The robustness of the results have been validated by means of Monte-Carlo simulations

An Op-Amp Approach for Bandpass VGAs With Constant Bandwidth

Two approaches to implement variable gain amplifiers based on Miller op-amps are discussed. One has true constant bandwidth while the other has essentially reduced bandwidth variations with varying gain. Servo-loops and ac coupling techniques with quasi floating gate transistors are used to provide a bandpass response with very low cutoff frequency in the range of hertz. In practice, one of the schemes is shown to have bandwidth variations close to a factor two while the second one has true constant bandwidth over the gain tuning range. Experimental results of test chip prototypes in 180-nm CMOS technology verify the theoretical claims