778 research outputs found
Scalable Successive-Cancellation Hardware Decoder for Polar Codes
Polar codes, discovered by Ar{\i}kan, are the first error-correcting codes
with an explicit construction to provably achieve channel capacity,
asymptotically. However, their error-correction performance at finite lengths
tends to be lower than existing capacity-approaching schemes. Using the
successive-cancellation algorithm, polar decoders can be designed for very long
codes, with low hardware complexity, leveraging the regular structure of such
codes. We present an architecture and an implementation of a scalable hardware
decoder based on this algorithm. This design is shown to scale to code lengths
of up to N = 2^20 on an Altera Stratix IV FPGA, limited almost exclusively by
the amount of available SRAM
Partial Sums Generation Architecture for Successive Cancellation Decoding of Polar Codes
Polar codes are a new family of error correction codes for which efficient
hardware architectures have to be defined for the encoder and the decoder.
Polar codes are decoded using the successive cancellation decoding algorithm
that includes partial sums computations. We take advantage of the recursive
structure of polar codes to introduce an efficient partial sums computation
unit that can also implements the encoder. The proposed architecture is
synthesized for several codelengths in 65nm ASIC technology. The area of the
resulting design is reduced up to 26% and the maximum working frequency is
improved by ~25%.Comment: Submitted to IEEE Workshop on Signal Processing Systems (SiPS)(26
April 2012). Accepted (28 June 2013
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