Strain engineered Si-Ge nanowire heterostructures and Josephson junction field-effect transistors for logic device applications

There has been relentless effort on the physical scaling of silicon (Si) metal-oxide-semiconductor field-effect transistors (MOSFETs) in pursuit of higher computing power in the past decades. Silicon and germanium (Ge) based nanowires are compatible with the standard Si process and promising for the ultimately scaled devices, by allowing the gate-all-around geometry and integration of strain engineering through radial heterostructures to address device-scaling limitations. In the first part of the thesis, advances in probing the strain of radial nanowire heterostructures and carrier mobility enhancement through strain engineering are presented. We present a sequence of structural characterization techniques for Ge-Si [subscript x] Ge [subscript 1-x] and Si-Si [subscript x] Ge [subscript 1-x] core-shell nanowires that extends to all types of Si-Ge radial nanowire heterostructures examined in the thesis. We combine planar and cross-sectional transmission electron microscopy to identify the crystal structure, orientation and morphology of the nanowire heterostructures. We then apply continuum elasticity model to calculate the strain distribution, which coupled with the lattice dynamic theory yields the Ge-Ge or Si-Si Raman modes under strain, showing good agreement with the experimental values acquired via Raman spectroscopy. We also study the electrical properties of Si [subscript x] Ge [subscript 1-x]-Si core-shell nanowires by fabricating and characterizing n-type MOSFETs, and show that the tensile strain in the Si shell leads to a 40% electron mobility enhancement compared to bare Si nanowire MOSFETs. Additionally, we demonstrate both n-type and p-type MOSFETs using Si [subscript x] Ge [subscript 1-x]-Ge-Si core-double-shell nanowires as channel, designed so that holes populate the Ge shell and electrons populate the Si shell, with mobility enhancement of both carriers thanks to the compressive and tensile strain in the respective region. We also extract the valence band offset from the decoupled hole transport in the two shells at low temperature, overcoming the issue that most techniques available to probe the band structure in planar heterostructures are not promptly applicable. Reducing the operation temperature provides an additional path for system optimization in addition to the shrinking of device geometry. In the second part of the thesis, we explore a Boolean logic device suitable for cryogenic computing. We execute a combined effort of modeling and experimental characterization to examine the feasibility of Josephson junction field-effect transistors (JJ-FETs) for logic device applications at low temperatures. JJ-FETs are similar to MOSFETs, with their source and drain electrodes being superconducting at the operation temperature. We develop a compact model for JJ-FETs operating in the short ballistic regime, and perform circuit level simulations to investigate the criteria of signal restoration and fan-out for JJ-FET logic gates. We also experimentally demonstrate the operation of JJ-FETs based on an InAs quantum well heterostructure platform. We perform self-consistent Poisson-Schrödinger simulations, finding different gate voltage regimes where carriers populate one or more subbands in different vertical positions of the heterostructure. Furthermore, we extend the short ballistic model to interpret the experimental data, and discuss the impact of a low oxide/channel interface quality on the implementation of practical JJ-FET logic devices.Electrical and Computer Engineerin

Scaling Properties of Ge-SixGe1-x Core-Shell Nanowire Field Effect Transistors

We demonstrate the fabrication of high-performance Ge-SixGe1-x core-shell nanowire field-effect transistors with highly doped source and drain, and systematically investigate their scaling properties. Highly doped source and drain regions are realized by low energy boron implantation, which enables efficient carrier injection with a contact resistance much lower than the nanowire resistance. We extract key device parameters, such as intrinsic channel resistance, carrier mobility, effective channel length, and external contact resistance, as well as benchmark the device switching speed and ON/OFF current ratio.Comment: 5 pages, 4 figures. IEEE Transactions on Electron Devices (in press

Performance Analysis of a Ge/Si Core/Shell Nanowire Field Effect Transistor

We analyze the performance of a recently reported Ge/Si core/shell nanowire transistor using a semiclassical, ballistic transport model and an sp3s*d5 tight-binding treatment of the electronic structure. Comparison of the measured performance of the device with the effects of series resistance removed to the simulated result assuming ballistic transport shows that the experimental device operates between 60 to 85% of the ballistic limit. For this ~15 nm diameter Ge nanowire, we also find that 14-18 modes are occupied at room temperature under ON-current conditions with ION/IOFF=100. To observe true one dimensional transport in a Ge nanowire transistor, the nanowire diameter would have to be much less than about 5 nm. The methodology described here should prove useful for analyzing and comparing on common basis nanowire transistors of various materials and structures

Core-Shell homojunction silicon vertical nanowire tunneling field-effect transistors

We propose three-terminal core-shell (CS) silicon vertical nanowire tunneling field-effect transistors (TFETs), which can be fabricated by conventional CMOS technology. CS TFETs show lower subthreshold swing (SS) and higher on-state current than conventional TFETs through their high surface-to-volume ratio, which increases carrier-tunneling region with no additional device area. The on-state current can be enhanced by increasing the nanowire height, decreasing equivalent oxide thickness (EOT) or creating a nanowire array. The off-state current is also manageable for power saving through selective epitaxial growth at the top-side nanowire region. CS TFETs with an EOT of 0.8 nm and an aspect ratio of 20 for the core nanowire region provide the largest drain current ranges with point SS values below 60 mV/dec and superior on/off current ratio under all operation voltages of 0.5, 0.7, and 1.0 V. These devices are promising for low-power applications at low fabrication cost and high device density.1130Ysciescopu

Doping Profiles in Ultrathin Vertical VLS-Grown InAs Nanowire MOSFETs with High Performance.

Thin vertical nanowires based on III-V compound semiconductors are viable candidates as channel material in metal oxide semiconductor field effect transistors (MOSFETs) due to attractive carrier transport properties. However, for improved performance in terms of current density as well as contact resistance, adequate characterization techniques for resolving doping distribution within thin vertical nanowires are required. We present a novel method of axially probing the doping profile by systematically changing the gate position, at a constant gate length L g of 50 nm and a channel diameter of 12 nm, along a vertical nanowire MOSFET and utilizing the variations in threshold voltage V T shift (∼100 mV). The method is further validated using the well-established technique of electron holography to verify the presence of the doping profile. Combined, device and material characterizations allow us to in-depth study the origin of the threshold voltage variability typically present for metal organic chemical vapor deposition (MOCVD)-grown III-V nanowire devices

Vertical Heterostructure III-V MOSFETs for CMOS, RF and Memory Applications

This thesis focuses mainly on the co-integration of vertical nanowiren-type InAs and p-type GaSb MOSFETs on Si (Paper I & II), whereMOVPE grown vertical InAs-GaSb heterostructure nanowires areused for realizing monolithically integrated and co-processed all-III-V CMOS.Utilizing a bottom-up approach based on MOVPE grown nanowires enablesdesign flexibilities, such as in-situ doping and heterostructure formation,which serves to reduce the amount of mask steps during fabrication. By refiningthe fabrication techniques, using a self-aligned gate-last process, scaled10-20 nm diameters are achieved for balanced drive currents at Ion ∼ 100μA/μm, considering Ioff at 100 nA/μm (VDD = 0.5 V). This is enabledby greatly improved p-type MOSFET performance reaching a maximumtransconductance of 260 μA/μm at VDS = 0.5 V. Lowered power dissipationfor CMOS circuits requires good threshold voltage VT matching of the n- andp-type device, which is also demonstrated for basic inverter circuits. Thevarious effects contributing to VT-shifts are also studied in detail focusing onthe InAs channel devices (with highest transconductance of 2.6 mA/μm), byusing Electron Holography and a novel gate position variation method (PaperV).The advancements in all-III-V CMOS integration spawned individual studiesinto the strengths of the n- and p-type III-V devices, respectively. Traditionallymaterials such as InAs and InGaAs provide excellent electrontransport properties, therefore they are frequently used in devices for highfrequency RF applications. In contrast, the III-V p-type alternatives have beenlacking performance mostly due to the difficult oxidation properties of Sb-based materials. Therefore, a study of the GaSb properties, in a MOSFETchannel, was designed and enabled by new manufacturing techniques, whichallowed gate-length scaling from 40 to 140 nm for p-type Sb-based MOSFETs(Paper III). The new fabrication method allowed for integration of deviceswith symmetrical contacts as compared to previous work which relied on atunnel-contact at the source-side. By modelling based on measured data fieldeffecthole mobility of 70 cm2/Vs was calculated, well in line with previouslyreported studies on GaSb nanowires. The oxidation properties of the GaSbgate-stack was further characterized by XPS, where high intensities of xraysare achieved using a synchrotron source allowed for characterization ofnanowires (Paper VI). Here, in-situ H2-plasma treatment, in parallel with XPSmeasurements, enabled a study of the time-dependence during full removalof GaSb native oxides.The last focus of the thesis was building on the existing strengths of verticalheterostructure III-V n-type (InAs-InGaAs graded channel) devices. Typically,these devices demonstrate high-current densities (gm >3 mS/μm) and excellentmodulation properties (off-state current down to 1 nA/μm). However,minimizing the parasitic capacitances, due to various overlaps originatingfrom a low access-resistance design, has proven difficult. Therefore, newmethods for spacers in both the vertical and planar directions was developedand studied in detail. The new fabrication methods including sidewall spacersachieved gate-drain capacitance CGD levels close to 0.2 fF/μm, which isthe established limit by optimized high-speed devices. The vertical spacertechnology, using SiO2 on the nanowire sidewalls, is further improved inthis thesis which enables new co-integration schemes for memory arrays.Namely, the refined sidewall spacer method is used to realize selective recessetching of the channel and reduced capacitance for large array memoryselector devices (InAs channel) vertically integrated with Resistive RandomAccess Memory (RRAM) memristors. (Paper IV) The fabricated 1-transistor-1-memristor (1T1R) demonstrator cell shows excellent endurance and retentionfor the RRAM by maintaining constant ratio of the high and low resistive state(HRS/LRS) after 106 switching cycles

Vertical III-V Nanowire Transistors for Low-Power Electronics

Power dissipation has been the major challenge in the downscaling of transistor technology. Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) have struggled to keep a low power consumption while still maintaining a high performance due to the low carrier mobilities of Si but also due to their inherent minimum inverse subthreshold slope (S ≥ 60 mV/dec) which is limited by thermionic emission. This thesis work studied the capabilities and limitations of III-V based vertical nanowire n-type Tunneling Field-Effect Transistor (TFET) and p-type MOSFET (PMOS). InAs/InGaAsSb/GaSb heterojunction was employed in the whole study. The main focus was to understand the influence of the device fabrication processes and the structural factors of the nanowires such as band alignment, composition and doping on the electrical performance of the TFET. Optimizations of the device processes including spacer technology improvement, Equivalent Oxide Thickness (EOT) downscaling, and gate underlap/overlap were explored utilizing structural characterizations. Systematic fine tuning of the band alignment of the tunnel junction resultedin achieving the best performing sub-40 mV/dec TFETs with S = 32 mV/decand ION = 4μA/μm for IOFF = 1 nA/μm at VDS = 0.3 V. The suitability of employing TFET for electronic applications at cryogenic temperatures has been explored utilizing experimental device data. The impact of the choice of heterostructure and dopant incorporation were investigated to identify the optimum operating temperature and voltage in different temperature regimes. A novel gate last process self-aligning the gate and drain contacts to the intrinsic and doped segments, respectively was developed for vertical InGaAsSb-GaAsSb core-shell nanowire transistors leading to the first sub-100 mV/dec PMOS with S = 75 mV/dec, significant ION/ IOFF = 104 and IMIN < 1 nA/μm at VDS = -0.5 V

Electric-field dependent g-factor anisotropy in Ge-Si core-shell nanowire quantum dots

We present angle-dependent measurements of the effective g-factor g* in a Ge-Si core-shell nanowire quantum dot. g* is found to be maximum when the magnetic field is pointing perpendicular to both the nanowire and the electric field induced by local gates. Alignment of the magnetic field with the electric field reduces g* significantly. g* is almost completely quenched when the magnetic field is aligned with the nanowire axis. These findings confirm recent calculations, where the obtained anisotropy is attributed to a Rashba-type spin-orbit interaction induced by heavy-hole light-hole mixing. In principle, this facilitates manipulation of spin-orbit qubits by means of a continuous high-frequency electric field