Digital fringe projection system for measuring warpage of painted and unpainted PBGAs and boards and FEA studies of PBGA warpage

Improvements in chip package technologies have led to smaller package sizes and higher density circuitry that require superior reliability of chip packages. One of the crucial factors affecting the reliability of chip packages is warpage which primarily occurs during the reflow process. Because warpage may cause serious reliability problems such as solder bump failure and die cracking, warpage control has become a crucial task. Advancements in warpage measurement and prediction would provide important steps toward addressing this concern. Among the various warpage measurement techniques, fringe projection techniques (i.e., laser fringe projection (LFP) and digital fringe projection (DFP)) have emerged as recent trends due to their non-contact, full-field, and high-resolution (for small viewing area) capabilities for measuring the warpage of chip packages and boards (i.e., printed wiring boards (PWBs) and PWB assemblies). In this research, the measurement capabilities of a LFP system were improved by reducing its laser speckle noise and post-processing time, and a novel DFP system for measuring the warpage of painted and unpainted chip packages and boards was developed. Also, parametric studies were performed to predict the warpage of plastic ball grid array packages affected by four geometric factors. Finally, a guideline that manufacturing engineers can use for selecting the most suitable warpage measurement technique for their particular application was developed. The results of this study will help to improve the yields and reliability of chip packages and boards, reduce the manufacturing costs and time to market for chip packages and boards and ultimately reduce the prices of end-products.Ph.D

Monolithic electronic-photonic integration in state-of-the-art CMOS processes

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Cataloged from student submitted PDF version of thesis.Includes bibliographical references (p. 388-407).As silicon CMOS transistors have scaled, increasing the density and energy efficiency of computation on a single chip, the off-chip communication link to memory has emerged as the major bottleneck within modern processors. Photonic devices promise to break this bottleneck with superior bandwidth-density and energy-efficiency. Initial work by many research groups to adapt photonic device designs to a silicon-based material platform demonstrated suitable independent performance for such links. However, electronic-photonic integration attempts to date have been limited by the high cost and complexity associated with modifying CMOS platforms suitable for modern high-performance computing applications. In this work, we instead utilize existing state-of-the-art electronic CMOS processes to fabricate integrated photonics by: modifying designs to match the existing process; preparing a design-rule compliant layout within industry-standard CAD tools; and locally-removing the handle silicon substrate in the photonic region through post-processing. This effort has resulted in the fabrication of seven test chips from two major foundries in 28, 45, 65 and 90 nm CMOS processes. Of these efforts, a single die fabricated through a widely available 45nm SOI-CMOS mask-share foundry with integrated waveguides with 3.7 dB/cm propagation loss alongside unmodified electronics with less than 5 ps inverter stage delay serves as a proof-of-concept for this approach. Demonstrated photonic devices include high-extinction carrier-injection modulators, 8-channel wavelength division multiplexing filter banks and low-efficiency silicon germanium photodetectors. Simultaneous electronic-photonic functionality is verified by recording a 600 Mb/s eye diagram from a resonant modulator driven by integrated digital circuits. Initial work towards photonic device integration within the peripheral CMOS flow of a memory process that has resulted in polysilicon waveguide propagation losses of 6.4 dB/cm will also be presented.by Jason S. Orcutt.Ph.D