Static noise analysis for digital integrated circuits in partially-depleted silicon-on-insulator technology

In this paper, we extend transistor-level static noise analysis tools to consider the unique features of partially-depleted silicon-oninsulator (PD-SOI) technology: floating-body-induced threshold voltage variations and parasitic bipolar leakage currents. This involves a unique state-diagram abstraction of the device physics determining the body-potential of PD-SOI FETs. Based on this picture, a simple model of the body voltage is derived which takes into account modest knowledge of which nets have dependable, regular switching activity. Results are presented using a commericial static noise analysis tool incorporating these extensions. Partially-depleted silicon-on-insulator (PD-SOI) has emerged as a leading technology for high-performance, low-power deepsubmicron digital integrated circuits[1, 2, 3, 4]. PD-SOI technology delivers two main advantages for digital applications: the reduction of the parasitic capacitance associated with source and drain diffusion