Identification of Soft-Error at Gate Level

Due to shrinking feature size and significant reduction in noise margins, as we are moving into very deep sub-micron technology, circuits have become more susceptible to manufacturing defects, noise-related transient faults and interference from radiation. Traditionally, soft errors have been a much greater concern in memories than in logic circuits. However, due to technology scaling, logic circuits have become equally susceptible to soft errors. Moreover, enhanced usage of commercial off the shelf (COTS) electronic components for avionics has also increased the importance of analyzing soft errors in hardware circuits. Conventionally, understanding soft error glitches requires circuit level modeling, which requires information available only at late stages in the design flow. Instead of this approach some researchers have produced modeling techniques using Reduced Order Binary Decision Diagrams (ROBDD) and Algebraic Decision Diagrams (ADD), which does allow analyzing soft error at an earlier stage in design flow. In this thesis, a new methodology for modeling soft errors glitch propagation path using Multiway Decision Graphs is introduced. This modeling technique is applicable on both combinational and asynchronous circuits. The proposed glitch propagation path modeling technique jointly takes care of logical and electrical masking. Our methodology involves new ways of injecting glitches including glitch injection in feedback paths of asynchronous circuits. This work presents a complete framework to exhaustively provide all the possible sequences of signals that lead to the possibility of glitch propagation to the primary output in combinational and asynchronous circuits. In addition, a new tool is developed based on the proposed methodology called Soft Error Glitch-Propagating Path Finder (SEGP-Finder) to automate the identification of these sequences of signals. This work helps designers identify the vulnerable circuit paths at the logic abstraction level. Also, this methodology allows designers to apply radiation tolerance techniques on reduced sets of possibilities. By applying our methodology on different combinational and asynchronous circuits an improvement in terms of possible-fault injection vectors is observed. As an example, approximately 8% of all the possible input vectors and sequences is required for obtaining exhaustive glitch propagation path identification in a representative implementation of a bundled data asynchronous circuit. To the best of our knowledge, this is the first time MDG based decision diagram based soft error identification approach is proposed for combinational and asynchronous circuits

Integrating SAT with MDG for Efficient Invariant Checking

Multiway Decision Graph (MDG) is a canonical representation of a subset of many-sorted first-order logic. It generalizes the logic of equality with abstract types and uninterpreted function symbols. The area of Satisfiability (SAT) has been the subject of intensive research in recent years, with significant theoretical and practical contributions. From a practical perspective, a large number of very effective SAT solvers have recently been proposed, most of which based on improvements made to the original Davis-Putnam algorithm. Local search algorithms have allowed solving extremely large satisfiable instances of SAT. The combination between various verification methodologies will enhance the capabilities of each and overcome their limitations. In this thesis, we introduce a methodology and propose a new design verification tool integrating MDG and SAT, to check the safety of a design by invariant checking. Using MDG to encode the set of states provide powerful mean of abstraction. We use SAT solver searching for paths of reachable states violating the property under certain encoding constraints. In addition, we also introduce an automated conversion-verification methodology to convert a Directed Formula (DF) into Conjunctive Normal Form (CNF) formula that can be fed to a SAT solver. The formal verification of this conversion is conducted within the HOL theorem prover. Finally, we implement and conduct experiment on some examples along with a case study to show the correctness and the efficiency of our approach