Software-controlled multithreading using informing memory operations

grantor: University of TorontoMemory latency is becoming an increasingly important performance bottleneck, especially in multiprocessors. One technique for tolerating memory latency is 'multithreading', whereby we switch between threads upon expensive cache misses. In contrast with previous work on multithreading, we explore a new approach that is 'software-controlled' rather than hardware-controlled. Our experimental results demonstrate that software-controlled multithreading can result in significant performance gains on a shared-memory multiprocessor, with the majority of applications speeding up by 10% or more, and one application speeding up by 16%. By selectively applying a ' register partitioning' optimization to reduce thread-switching overhead, the overall speedups increase to as much as 25%. Given the much simpler hardware support required by our scheme, and the fact that its software overheads are expected to become less and less expensive over time relative to memory latencies, software-controlled multithreading is attractive alternative to traditional hardware-based schemes.M.A.Sc

Software-controlled multithreading using informing memory operations

Memory latency is becoming an increasingly important performance bottleneck, especially in multiprocessors. One technique for tolerating memory latency is multithreading, whereby we switch between threads upon expensive cache misses. In contrast with previous work on multithreading, we explore a new approach that is software-controlled rather than hardware-controlled. To implement software-controlled multithreading, we use informing memory operations to quickly trap upon cache misses to a miss handler which performs the actual thread switching in software. Our experimental results demonstrate that software-controlled multithreading can result in signi cant performance gains on a shared-memory multiprocessor, with the majority of applications speeding up by 10 % or more, and one application speeding up by 16%. In addition, we nd that by selectively applying a register partitioning optimization to reduce the thread-switching overhead, we can increase the overall speedups to as much as 25%. Given the much simpler hardware support required by our scheme, and the fact that its software overheads are expected to become less and less expensive over time relative to memory latencies, software-controlled multithreading is attractive alternative to traditional hardware-based schemes