56 research outputs found

    Reconfigurable Architecture for Noise Cancellation in Acoustic Environment Using Single Multiply Accumulate Adaline Filter

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    The creation of multiple applications with a higher level of complexity has been made possible by the usage of artificial neural networks (ANNs). In this research, an efficient flexible finite impulse response (FIR) filter structure called ADALINE (adaptive linear element) that makes use of a MAC (multiply accumulate) core is proposed. The least mean square (LMS) and recursive least square (RLS) algorithms are the most often used methods for maximizing filter coefficients. Despite outperforming the LMS, the RLS approach has not been favored for real-time applications due to its higher design arithmetic complexity. To achieve less computation, the fundamental filter has utilized an LMS-based tapping delay line filter, which is practically a workable option for an adaptive filtering algorithm. To discover the undiscovered system, the adjustable coefficient filters have been developed in the suggested work utilizing an optimal LMS approach. The 10-tap filter being considered here has been analyzed and synthesized utilizing field programmable gate array (FPGA) devices and programming in hardware description language. In terms of how well the resources were used, the placement and postrouting design performed well. If the implemented filter architecture is compared with the existing filter architecture, it reveals a 25% decrease in resources from the existing one and an increase in clock frequency of roughly 20%

    Multifunction Radios and Interference Suppression for Enhanced Reliability and Security of Wireless Systems

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    Wireless connectivity, with its relative ease of over-the-air information sharing, is a key technological enabler that facilitates many of the essential applications, such as satellite navigation, cellular communication, and media broadcasting, that are nowadays taken for granted. However, that relative ease of over-the-air communications has significant drawbacks too. On one hand, the broadcast nature of wireless communications means that one receiver can receive the superposition of multiple transmitted signals. But on the other hand, it means that multiple receivers can receive the same transmitted signal. The former leads to congestion and concerns about reliability because of the limited nature of the electromagnetic spectrum and the vulnerability to interference. The latter means that wirelessly transmitted information is inherently insecure. This thesis aims to provide insights and means for improving physical layer reliability and security of wireless communications by, in a sense, combining the two aspects above through simultaneous and same frequency transmit and receive operation. This is so as to ultimately increase the safety of environments where wireless devices function or where malicious wirelessly operated devices (e.g., remote-controlled drones) potentially raise safety concerns. Specifically, two closely related research directions are pursued. Firstly, taking advantage of in-band full-duplex (IBFD) radio technology to benefit the reliability and security of wireless communications in the form of multifunction IBFD radios. Secondly, extending the self-interference cancellation (SIC) capabilities of IBFD radios to multiradio platforms to take advantage of these same concepts on a wider scale. Within the first research direction, a theoretical analysis framework is developed and then used to comprehensively study the benefits and drawbacks of simultaneously combining signals detection and jamming on the same frequency within a single platform. Also, a practical prototype capable of such operation is implemented and its performance analyzed based on actual measurements. The theoretical and experimental analysis altogether give a concrete understanding of the quantitative benefits of simultaneous same-frequency operations over carrying out the operations in an alternating manner. Simultaneously detecting and jamming signals specifically is shown to somewhat increase the effective range of a smart jammer compared to intermittent detection and jamming, increasing its reliability. Within the second research direction, two interference mitigation methods are proposed that extend the SIC capabilities from single platform IBFD radios to those not physically connected. Such separation brings additional challenges in modeling the interference compared to the SIC problem, which the proposed methods address. These methods then allow multiple radios to intentionally generate and use interference for controlling access to the electromagnetic spectrum. Practical measurement results demonstrate that this effectively allows the use of cooperative jamming to prevent unauthorized nodes from processing any signals of interest, while authorized nodes can use interference mitigation to still access the same signals. This in turn provides security at the physical layer of wireless communications

    Cancellazione dell'eco acustica mediante filtraggio adattativo NLMS a filtri FIR e implementazione su DSP

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    Implementazione su DSP di un cancellatore di eco acustico basato sull'algoritmo NLMS a filtri FIR. Si è impiegato un ambiente di sviluppo grafico il PurePath Graph Studio della T.I. ai fini della programmazione della board. La soluzione è stata proposta per risolvere il problema di accoppiamento acustico tra lo speaker e il microfono presenti su dispositivi touchscreen operanti in impianti domoticiope

    KAVUAKA: a low-power application-specific processor architecture for digital hearing aids

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    The power consumption of digital hearing aids is very restricted due to their small physical size and the available hardware resources for signal processing are limited. However, there is a demand for more processing performance to make future hearing aids more useful and smarter. Future hearing aids should be able to detect, localize, and recognize target speakers in complex acoustic environments to further improve the speech intelligibility of the individual hearing aid user. Computationally intensive algorithms are required for this task. To maintain acceptable battery life, the hearing aid processing architecture must be highly optimized for extremely low-power consumption and high processing performance.The integration of application-specific instruction-set processors (ASIPs) into hearing aids enables a wide range of architectural customizations to meet the stringent power consumption and performance requirements. In this thesis, the application-specific hearing aid processor KAVUAKA is presented, which is customized and optimized with state-of-the-art hearing aid algorithms such as speaker localization, noise reduction, beamforming algorithms, and speech recognition. Specialized and application-specific instructions are designed and added to the baseline instruction set architecture (ISA). Among the major contributions are a multiply-accumulate (MAC) unit for real- and complex-valued numbers, architectures for power reduction during register accesses, co-processors and a low-latency audio interface. With the proposed MAC architecture, the KAVUAKA processor requires 16 % less cycles for the computation of a 128-point fast Fourier transform (FFT) compared to related programmable digital signal processors. The power consumption during register file accesses is decreased by 6 %to 17 % with isolation and by-pass techniques. The hardware-induced audio latency is 34 %lower compared to related audio interfaces for frame size of 64 samples.The final hearing aid system-on-chip (SoC) with four KAVUAKA processor cores and ten co-processors is integrated as an application-specific integrated circuit (ASIC) using a 40 nm low-power technology. The die size is 3.6 mm2. Each of the processors and co-processors contains individual customizations and hardware features with a varying datapath width between 24-bit to 64-bit. The core area of the 64-bit processor configuration is 0.134 mm2. The processors are organized in two clusters that share memory, an audio interface, co-processors and serial interfaces. The average power consumption at a clock speed of 10 MHz is 2.4 mW for SoC and 0.6 mW for the 64-bit processor.Case studies with four reference hearing aid algorithms are used to present and evaluate the proposed hardware architectures and optimizations. The program code for each processor and co-processor is generated and optimized with evolutionary algorithms for operation merging,instruction scheduling and register allocation. The KAVUAKA processor architecture is com-pared to related processor architectures in terms of processing performance, average power consumption, and silicon area requirements

    CABE : a cloud-based acoustic beamforming emulator for FPGA-based sound source localization

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    Microphone arrays are gaining in popularity thanks to the availability of low-cost microphones. Applications including sonar, binaural hearing aid devices, acoustic indoor localization techniques and speech recognition are proposed by several research groups and companies. In most of the available implementations, the microphones utilized are assumed to offer an ideal response in a given frequency domain. Several toolboxes and software can be used to obtain a theoretical response of a microphone array with a given beamforming algorithm. However, a tool facilitating the design of a microphone array taking into account the non-ideal characteristics could not be found. Moreover, generating packages facilitating the implementation on Field Programmable Gate Arrays has, to our knowledge, not been carried out yet. Visualizing the responses in 2D and 3D also poses an engineering challenge. To alleviate these shortcomings, a scalable Cloud-based Acoustic Beamforming Emulator (CABE) is proposed. The non-ideal characteristics of microphones are considered during the computations and results are validated with acoustic data captured from microphones. It is also possible to generate hardware description language packages containing delay tables facilitating the implementation of Delay-and-Sum beamformers in embedded hardware. Truncation error analysis can also be carried out for fixed-point signal processing. The effects of disabling a given group of microphones within the microphone array can also be calculated. Results and packages can be visualized with a dedicated client application. Users can create and configure several parameters of an emulation, including sound source placement, the shape of the microphone array and the required signal processing flow. Depending on the user configuration, 2D and 3D graphs showing the beamforming results, waterfall diagrams and performance metrics can be generated by the client application. The emulations are also validated with captured data from existing microphone arrays.</jats:p

    Heterogeneous wireless networks for smart cities

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    In the near future, a world of smart cities is envisioned in which many devices equipped with sensors and communication interfaces can be used to collect and share data in order to derive maps or infer information on some parameter of interest. Wireless technologies are enabling this smart city paradigms, where many items are networked for the growth of society. This scenario opens new challenges to wireless network designers, with new performance metrics, coverage and privacy needs, as well as the need for a tighter integration of different networks. This is the fundamental concept of Heterogeneous Networks. Enclosing humans in the loop, through crowdsensing techniques, will dramatically increase the amount of data available for the mapping process, with obvious benefits in terms of the resulting accuracy. On the other hand, the huge amount of data generated represents also a challenge that, along with the irregular, uncontrollable, spatial distribution of measurements represent serious challenges to be addressed. Another important aspect of smart cities scenarios is represented by vehicular networks. Several technologies have been proposed to address such application. Among the others, an interesting solution is provided by Visible Light Communications (VLC). Based on the use of the light emission diodes (LEDs) that are already available on the majority of vehicles, VLC would enable short range communication in large, unlicensed, and uncongested bands with limited costs. In the framework of smart cities scenarios, my research activity aimed at formulating and solving some of the issues arising from the envisioned challenging services, with both analytical and simulation-based approaches

    Abstracts on Radio Direction Finding (1899 - 1995)

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    The files on this record represent the various databases that originally composed the CD-ROM issue of "Abstracts on Radio Direction Finding" database, which is now part of the Dudley Knox Library's Abstracts and Selected Full Text Documents on Radio Direction Finding (1899 - 1995) Collection. (See Calhoun record https://calhoun.nps.edu/handle/10945/57364 for further information on this collection and the bibliography). Due to issues of technological obsolescence preventing current and future audiences from accessing the bibliography, DKL exported and converted into the three files on this record the various databases contained in the CD-ROM. The contents of these files are: 1) RDFA_CompleteBibliography_xls.zip [RDFA_CompleteBibliography.xls: Metadata for the complete bibliography, in Excel 97-2003 Workbook format; RDFA_Glossary.xls: Glossary of terms, in Excel 97-2003 Workbookformat; RDFA_Biographies.xls: Biographies of leading figures, in Excel 97-2003 Workbook format]; 2) RDFA_CompleteBibliography_csv.zip [RDFA_CompleteBibliography.TXT: Metadata for the complete bibliography, in CSV format; RDFA_Glossary.TXT: Glossary of terms, in CSV format; RDFA_Biographies.TXT: Biographies of leading figures, in CSV format]; 3) RDFA_CompleteBibliography.pdf: A human readable display of the bibliographic data, as a means of double-checking any possible deviations due to conversion

    Full Duplex CMOS Transceiver with On-Chip Self-Interference Cancelation

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    abstract: The demand for the higher data rate in the wireless telecommunication is increasing rapidly. Providing higher data rate in cellular telecommunication systems is limited because of the limited physical resources such as telecommunication frequency channels. Besides, interference with the other users and self-interference signal in the receiver are the other challenges in increasing the bandwidth of the wireless telecommunication system. Full duplex wireless communication transmits and receives at the same time and the same frequency which was assumed impossible in the conventional wireless communication systems. Full duplex wireless communication, compared to the conventional wireless communication, doubles the channel efficiency and bandwidth. In addition, full duplex wireless communication system simplifies the reusing of the radio resources in small cells to eliminate the backhaul problem and simplifies the management of the spectrum. Finally, the full duplex telecommunication system reduces the costs of future wireless communication systems. The main challenge in the full duplex wireless is the self-interference signal at the receiver which is very large compared to the receiver noise floor and it degrades the receiver performance significantly. In this dissertation, different techniques for the antenna interface and self-interference cancellation are proposed for the wireless full duplex transceiver. These techniques are designed and implemented on CMOS technology. The measurement results show that the full duplex wireless is possible for the short range and cellular wireless communication systems.Dissertation/ThesisDoctoral Dissertation Engineering 201

    Survey of FPGA applications in the period 2000 – 2015 (Technical Report)

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    Romoth J, Porrmann M, Rückert U. Survey of FPGA applications in the period 2000 – 2015 (Technical Report).; 2017.Since their introduction, FPGAs can be seen in more and more different fields of applications. The key advantage is the combination of software-like flexibility with the performance otherwise common to hardware. Nevertheless, every application field introduces special requirements to the used computational architecture. This paper provides an overview of the different topics FPGAs have been used for in the last 15 years of research and why they have been chosen over other processing units like e.g. CPUs
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