Design and simulation of strained-Si/strained-SiGe dual channel hetero-structure MOSFETs

With a unified physics-based model linking MOSFET performance to carrier mobility and drive current, it is shown that nearly continuous carrier mobility increase has been achieved by introduction of process-induced and global-induced strain, which has been responsible for increase in device performance commensurately with scaling. Strained silicon-germanium technology is a hot research area, explored by many different research groups for present and future CMOS technology, due to its high hole mobility and easy process integration with silicon. Several heterostructure architectures for strained Si/SiGe have been shown in the literature. A dual channel heterostructure consisting of strained Si/Si1-xGex on a relaxed SiGe buffer provides a platform for fabricating MOS transistors with high drive currents, resulting from high carrier mobility and carrier velocity, due to presence of compressively strained silicon germanium layer. This works reports the design, modeling and simulation of NMOS and PMOS transistors with a tensile strained Si channel layer and compressively strained SiGe channel layer for a 65 nm logic technology node. Since most of the recent work on development of strained Si/SiGe has been experimental in nature, developments of compact models are necessary to predict the device behavior. A unified modeling approach consisting of different physics-based models has been formulated in this work and their ability to predict the device behavior has been investigated. In addition to this, quantum mechanical simulations were performed in order to investigate and model the device behavior. High p/n-channel drive currents of 0.43 and 0.98 mA/Gm, respectively, are reported in this work. However with improved performance, ~ 10% electrostatic degradation was observed in PMOS due to buried channel device

The study of SiGe-channel heterojunction MOS device

The advances in the growth of pseudomorphic silicon-germanium epitaxial layer combined with the strong need for high-speed CMOS VLSI circuit have led to increased interest in silicon-based heterojunction MOSFET\u27s transistors. The high-performance heterostructure SiGe MOSFET exhibits higher channel mobility than its bulk Si counterpart. The most critical and challenging process for fabricating a SiGe MOSFET device is that for making a gate oxide with sufficient quality for useful conductivity modulation. PECVD methods was employed to deposit the gate oxide and C-V method was used to investigate the electrical characteristics of the film. For PECVD gate oxide, a film refractive index 1.47 were obtained using the deposition rate 125Å/min with a break down voltage 4-5 MV/cm, which deposition conditions are optimized as flow rate of DES (12sccm), N20(172sccm), Helium(850sccm), temperature 300°C, power density 0.09W/cm2. The total interface trap and fixed charge density Nt=5.4x1012 cm-2 and flatband voltage Vfb=-16V for non-armealing MOS capacitor and the total effect of interface trap and fixed charge density 6.4x1011 cm-2 and flatband voltage 4V were obtained at the oxide thickness dox=1160Å using annealing at 650°C for 30 minutes in the ambient of nitrogen. LPCVD silicon dioxide film was obtained at the deposition rate 14.5 Å/min and refractive index 1.46 while Nt=3.9x1012cm-2 and Vfb=-8V for nonannealing and Nt=4.9x1011 cm-2 and Vfb=-2V for 650°C annealed MOS capacitor

Silicon-Germanium Photodetectors for Optical Telecommunications

This thesis investigates the design and growth of silicon-germanium p-i-n photodetectors for optical telecommunications applications. Two types of heterostructures are considered: strained silicon-germanium layers grown directly on silicon substrates, and strain-balanced silicon-germanium/silicon superlattice grown on relaxed buffer layers. The heterostructures are designed using existing band structure models and are grown using solid source molecular beam epitaxy (SS-MBE). To facilitate these growths, an atomic absorption spectroscopy- based flux monitor for the silicon source is developed and calibrated. In addition, the development of a substrate preparation procedure for relaxed buffer layers that is compatible with SS-MBE is developed and allows the growth of epitaxial films with low defect densities. P-i-n diodes processed from these films are shown to have low reverse leakage currents densities compared to other competing devices. Photocurrent spectroscopy is used to characterize these structures. A clear reduction in the bandgap of the heterostructures over that of the constituent alloys due to exploitation of the Type-II band offsets in the silicon-germanium material system is demonstrated in both, the strained and strain-balanced photodetectors. Finally, the low leakage current densities are exploited to fabricate devices with noise equivalent powers comparable to or better than competing approaches based on the growth of germanium on silicon substrates

SiGe nanostructures: new insights into growth processes

International audienceDuring the last decade, Si/Si 1−x Ge x heterostructures have emerged as a viable system for use in CMOS technology with the recent industrial production of heterojunction bipolar transistor-based integrated circuits. However, many key problems have to be solved to further expand the capabilities of this system to other more attractive devices. This paper gives a comprehensive review of the progress achieved during the last few years in the understanding of some fundamental growth mechanisms. The discrepancies between classical theories (in the framework of continuum elasticity) and experimental results are also specially addressed. In particular, the major role played by kinetics in the morphological evolution of layers is particularly emphasized. Starting from the unexpected differences in Si 1−x Ge x morphological evolution when deposited on (001) and on (111), our review then focuses on: (1) the strain control and adjustment (from fully strained to fully relaxed 2D and 3D nanostructures)-in particular, some original examples of local CBED stress measurements are presented; (2) the nucleation, growth, and self-assembly processes, using self-patterned template layers and surfactant-mediated growth; (3) the doping processes (using B for type p and Sb for type n) and the limitations induced by dopant redistribution during and after growth due to diffusion, segregation, and desorption. The final section will briefly address some relevant optical properties of Si 1−x Ge x strained layers using special growth processes

Optimisation studies on strain-engineered Germanium heterostructures

The physical gate lengths of state-of-the-art CMOS devices are 45 nm and are anticipated to reach just 20 nm by 2007. Due to the prohibitive capital expenditure required for next-generation CMOS technologies, leading device manufacturers are now exploring exotic device architectures and novel substrates in which significant device performance enhancements may by obtained using the existing device fabrication infrastructure. This thesis reports studies made on an initial evaluation of hole transport properties in strained Ge channels and comprises physical and electrical characterisation of these heterostructures as well as the analysis of SiGe layers using secondary ion mass spectrometry. The initial work of thesis describes the growth, characterisation and optimisation of a novel strained Ge substrate. The substrate technology was developed using a hybrid-epitaxy technique in which a SiGe strain-relaxed buffer layer, so called "virtual substrate", was grown using a ultra-high vacuum chemical-vapour deposition growth technique and the active strained Ge layer was grown using a solid-source molecular-beam epitaxy growth technology. An advanced chemical cleaning procedure has been developed which includes a modified Piranha etch. The novel cleaning procedure enables the successful integration of the two growth techniques. Significant hole carrier transport enhancements were observed for holes contained within the strained Ge channel. Optimisation of the hole mobility was achieved by the reduction of carrier scattering such as interface roughness scattering and point defect scattering. The optimisation methods employed included growth temperature iterations to reduce Ge channel roughening via elastic relaxation and, channel thickness iterations were also employed in order to minimize channel roughening and defect nucleation. Post-growth annealing procedures were used to combat defects arising from low temperature growth. The Ge heterostructures were grown on strain relaxed buffer layers, terminating with a Ge content of 60%. The optimised strained Ge channel thickness was found to be 20 nm and the growth temperature of the active layers was reduced to 350°C so as to minimise surface roughening. As grown point defects were eliminated at an optimised post-growth anneal temperature of 650°C for 30 minutes under dry N2• Hall mobilities reached 1910 cm2Ns at room temperature rising to 26,900 cm2Ns at 10K. A magneto-conductivity transfonnation measurement and maximum entropy mobility spectrum analysis revealed a room temperature drift mobility of 2700 cm2Ns at a carrier density of l.Ox1012 cm-2 . This result represents a 15-fo1d increase in hole mobility compared to conventional Si substrates at comparable effective fields. The second and important part of this thesis addresses charging effects observed when profiling undoped SiGe layers and the quantification of Ge fraction within SiGe layers using secondary ion mass spectrometry. Due to the highly resistive spreading resistance found for undoped SiGe layers when profiled using an O2+ incident beam, charging effects were found to mask the true layer profile. In order to overcome this problem a new approach is discussed for the first time. By illuminating the sample with a red laser light (wavelength 635mn) electron-hole pairs were created via photon absorption. The excess charge carriers were sufficient to overcome localised charging effects induced by the primary ion beam during SIMS analysis. In this manner, total charge suppression was achieved, thereby enabling a true determination of the SiGe sample profile to be obtained via SIMS. Finally, an analytical method enabling the accurate determination of Ge content of SiGe layers is discussed. The method employs a comparative ion yield methodology and enables both the spatial distribution and Ge concentration of SiGe layers to be accurately determined from a single SIMS measurement