Power Side Channels in Security ICs: Hardware Countermeasures

Power side-channel attacks are a very effective cryptanalysis technique that can infer secret keys of security ICs by monitoring the power consumption. Since the emergence of practical attacks in the late 90s, they have been a major threat to many cryptographic-equipped devices including smart cards, encrypted FPGA designs, and mobile phones. Designers and manufacturers of cryptographic devices have in response developed various countermeasures for protection. Attacking methods have also evolved to counteract resistant implementations. This paper reviews foundational power analysis attack techniques and examines a variety of hardware design mitigations. The aim is to highlight exposed vulnerabilities in hardware-based countermeasures for future more secure implementations

Geoengineering: A war on climate change?

Geoengineering; specifically Solar Radiation Management ; has been proposed to effect rapid influence over the Earth’s climate system in order to counteract Anthropogenic Global Warming. This poses near-term to long-term governance challenges; some of which are within the planning horizon of current political administrations. Previous discussions of governance of SRM have focused primarily on two scenarios: an isolated “Greenfinger” individual; or state; acting independently ; versus more consensual; internationalist approaches. I argue that these models represent a very limited sub-set of plausible deployment scenarios. To generate a range of alternative models; I offer a short; relatively unstructured discussion of a range of different types of warfare – each with an analogous SRM deployment regime

A low cost solution to authentication in passive RFID systems

Auto-ID Lab University of Adelaide (c) 2006 Copyright. The document attached has been archived with permission.This paper aims to propose a solution to address the issue of authentication to prevent counterfeiting in a low cost RFID based system based on using Physically Uncloneable Functions.Damith C. Ranasinghe, Daihyun Lim, Peter H. Cole and Srinivas Devada

Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library

MOS Current Mode Logic (MCML) is one of the most promising logic style to counteract power analysis attacks. Unfortunately, the static power consumption of MCML standard cells is significantly higher compared to equivalent functions implemented using static CMOS logic. As a result, the use of such a logic style is very limited in portable devices. Paradoxically, these devices are the most sensitive to physical attacks, thus the ones which would benefit more from the adoption of MCML

Transmission gate based dual rail logic for differential power analysis resistant circuits

Cryptographic devices with hardware implementation of the algorithms are increasingly being used in various applications. As a consequence, there is an increased need for security against the attacks on the cryptographic system. Among various attack techniques, side channel attacks pose a significant threat to the hardware implementation. Power analysis attacks are a type of side channel attack where the power leakage from the underlying hardware is used to eavesdrop on the hardware operation. Wave pipelined differential and dynamic logic (WDDL) has been found to be an effective countermeasure to power analysis. This thesis studies the use of transmission gate based WDDL implementation for the differential and dynamic logic. Although WDDL is an effective defense against power analysis, the number of gates needed for the design of a secure implementation is double the number of gates used for non-secure operations. In this thesis we propose transmission gate based structures for implementation of wave pipelined dynamic and differential logic to minimize the overhead of this defense against power analysis attacks. A transmission gate WDDL design methodology is presented, and the design and analysis of a secure multiplier is given. The adder structures are compared in terms of security effectiveness and silicon area overhead for three cases: unsecured logic implementation, standard gate WDDL, and transmission gate WDDL. In simulation, the transmission gate WDDL design is seen to have similar power consumption results compared to the standard gate WDDL; however, the transmission gate based circuit uses 10-50% fewer gates compared to the static WDDL

Side-channel attacks and countermeasures in the design of secure IC's devices for cryptographic applications

Abstract--- A lot of devices which are daily used have to guarantee the retention of sensible data. Sensible data are ciphered by a secure key by which only the key holder can get the data. For this reason, to protect the cipher key against possible attacks becomes a main issue. The research activities in hardware cryptography are involved in finding new countermeasures against various attack scenarios and, in the same time, in studying new attack methodologies. During the PhD, three different logic families to counteract Power Analysis were presented and a novel class of attacks was studied. Moreover, two different activities related to Random Numbers Generators have been addressed

Using embedded hardware monitor cores in critical computer systems

The integration of FPGA devices in many different architectures and services makes monitoring and real time detection of errors an important concern in FPGA system design. A monitor is a tool, or a set of tools, that facilitate analytic measurements in observing a given system. The goal of these observations is usually the performance analysis and optimisation, or the surveillance of the system. However, System-on-Chip (SoC) based designs leave few points to attach external tools such as logic analysers. Thus, an embedded error detection core that allows observation of critical system nodes (such as processor cores and buses) should enforce the operation of the FPGA-based system, in order to prevent system failures. The core should not interfere with system performance and must ensure timely detection of errors. This thesis is an investigation onto how a robust hardware-monitoring module can be efficiently integrated in a target PCI board (with FPGA-based application processing features) which is part of a critical computing system. [Continues.

Time-bin entanglement at telecom wavelengths from a hybrid photonic integrated circuit

Mass-deployable implementations for quantum communication require compact, reliable, and low-cost hardware solutions for photon generation, control and analysis. We present a fiber-pigtailed hybrid photonic circuit comprising nonlinear waveguides for photon-pair generation and a polymer interposer reaching 68dB of pump suppression and photon separation with >25dB polarization extinction ratio. The optical stability of the hybrid assembly enhances the quality of the entanglement, and the efficient background suppression and photon routing further reduce accidental coincidences. We thus achieve a 96(-8,+3)% concurrence and a 96(-5,+2)% fidelity to a Bell state. The generated telecom-wavelength, time-bin entangled photon pairs are ideally suited for distributing Bell pairs over fiber networks with low dispersion