Radix-2n serial–serial multipliers

All serial–serial multiplication structures previously reported in the literature have been confined to bit serial–serial multipliers. An architecture for digit serial–serial multipliers is presented. A set of designs are derived from the radix-2n design procedure, which was first reported by the authors for the design of bit level pipelined digit serial–parallel structures. One significant aspect of the new designs is that they can be pipelined to the bit level and give the designer the flexibility to obtain the best trade-off between throughput rate and hardware cost by varying the digit size and the number of pipelining levels. Also, an area-efficient digit serial–serial multiplier is proposed which provides a 50% reduction in hardware without degrading the speed performance. This is achieved by exploiting the fact that some cells are idle for most of the multiplication operation. In the new design, the computations of these cells are remapped to other cells, which make them redundant. The new designs have been implemented on the S40BG256 device from the SPARTAN family to prove functionality and assess performance

Memory device for two-dimensional radiant energy array computers

A memory device for two dimensional radiant energy array computers was developed, in which the memory device stores digital information in an input array of radiant energy digital signals that are characterized by ordered rows and columns. The memory device contains a radiant energy logic storing device having a pair of input surface locations for receiving a pair of separate radiant energy digital signal arrays and an output surface location adapted to transmit a radiant energy digital signal array. A regenerative feedback device that couples one of the input surface locations to the output surface location in a manner for causing regenerative feedback is also include

Bit-level pipelined digit-serial array processors

A new architecture for high performance digit-serial vector inner product (VIP) which can be pipelined to the bit-level is introduced. The design of the digit-serial vector inner product is based on a new systematic design methodology using radix-2n arithmetic. The proposed architecture allows a high level of bit-level pipelining to increase the throughput rate with minimum initial delay and minimum area. This will give designers greater flexibility in finding the best tradeoff between hardware cost and throughput rate. It is shown that sub-digit pipelined digit-serial structure can achieve a higher throughput rate with much less area consumption than an equivalent bit-parallel structure. A twin-pipe architecture to double the throughput rate of digit-serial multipliers and consequently that of the digit-serial vector inner product is also presented. The effect of the number of pipelining levels and the twin-pipe architecture on the throughput rate and hardware cost are discussed. A two's complement digit-serial architecture which can operate on both negative and positive numbers is also presented

Step response of a second-order digital filter with two’s complement arithmetic

It is well known that the autonomous response of a second-order digital filter with two’s complement arithmetic may exhibit chaotic behaviors [1]. In this paper, results of the step response case are presented. Even though in the presence of the overflow nonlinearity, it is found that the step response behaviors can be related to some corresponding autonomous response behaviors by means of an appropriate affine transformation. Based on this method, some differences between the step response and the autonomous response are explored. The effects of the filter parameter and input step size on the trajectory behaviors are presented. Some previous necessary conditions for the trajectory behaviors, initial conditions and symbolic sequences are extended and strengthened to become necessary and sufficient conditions. Based on these necessary and sufficient conditions, some counter-intuitive results are reported. For example, it is found that for some sets of filter parameter values, the system may exhibit the type I trajectory even when a large input step size is applied and overflow occurs. On the other hand, for some sets of filter parameter values, the system will not give the type I trajectory for any small input step size, no matter what the initial conditions are

E-Learning Strategies in Developing Research Performance Efficiency: Higher Education Institutions

The study aimed to identify E- Learning strategies and their relation to the efficiency of research performance in foreign and Palestinian universities (University of Ottawa, Munster, Suez Canal, Al-Azhar, Islamic, Al-Aqsa). The analytical descriptive approach was used for this purpose, and relying on the questionnaire as a main tool for data collection. The study society is from the senior management, where the number of senior management in the universities in question is 206. The random stratified sample was selected and (SPSS) was used for statistical data analysis. The study found a significant relationship between E- Learning strategies and the efficiency of research performance in universities. It also reached the participation of senior management in the research that develops the university performance in the Palestinian universities. The senior management indicated that they do not care to follow the policies of implementing the development of scientific research. While the senior management in foreign universities indicated that they are interested in following up the policies of implementing the development of scientific research. The study also showed that senior management in Palestinian universities does not care about providing the appropriate budget for E- Learning. The study recommended that the senior management of Palestinian universities should provide an E- Learning budget and encourage employees to continue using E- Learning strategies. The administration in the Palestinian universities should adopt and support outstanding research, and the need to encourage interest in the implementation of policies for the development of scientific research