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    ๋†’์€ ์ „๋ฅ˜ ๊ตฌ๋™๋Šฅ๋ ฅ์„ ๊ฐ€์ง€๋Š” SiGe ๋‚˜๋…ธ์‹œํŠธ ๊ตฌ์กฐ์˜ ํ„ฐ๋„๋ง ์ „๊ณ„ํšจ๊ณผ ํŠธ๋žœ์ง€์Šคํ„ฐ

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    ํ•™์œ„๋…ผ๋ฌธ (๋ฐ•์‚ฌ) -- ์„œ์šธ๋Œ€ํ•™๊ต ๋Œ€ํ•™์› : ๊ณต๊ณผ๋Œ€ํ•™ ์ „๊ธฐยท์ •๋ณด๊ณตํ•™๋ถ€, 2021. 2. ๋ฐ•๋ณ‘๊ตญ.The development of very-large-scale integration (VLSI) technology has continuously demanded smaller devices to achieve high integration density for faster computing speed or higher capacity. However, in the recent complementary-metal-oxide-semiconductor (CMOS) technology, simple downsizing the dimension of metal-oxide-semiconductor field-effect transistor (MOSFET) no longer guarantees the boosting performance of IC chips. In particular, static power consumption is not reduced while device size is decreasing because voltage scaling is slowed down at some point. The increased off-current due to short-channel effect (SCE) of MOSFET is a representative cause of the difficulty in voltage scaling. To overcome these fundamental limits of MOSFET, many researchers have been looking for the next generation of FET device over the last ten years. Tunnel field-effect transistor (TFET) has been intensively studied for its steep switching characteristics. Nevertheless, the poor current drivability of TFET is the most serious obstacle to become competitive device for MOSFET. In this thesis, TFET with high current drivability in which above-mentioned problem is significantly solved is proposed. Vertically-stacked SiGe nanosheet channels are used to boost carrier injection and gate control. The fabrication technique to form highly-condensed SiGe nanosheets is introduced. TFET is fabricated with MOSFET with the same structure in the CMOS-compatible process. Both technology-computer-aided-design (TCAD) simulation and experimental results are utilized to support and examine the advantages of proposed TFET. From the perspective of the single device, the improvement in switching characteristics and current drivability are quantitatively and qualitatively analyzed. In addition, the device performance is compared to the benchmark of previously reported TFET and co-fabricated MOSFET. Through those processes, the feasibility of SiGe nanosheet TFET is verified. It is revealed that the proposed SiGe nanosheet TFET has notable steeper switching and low leakage in the low drive voltage as an alternative to conventional MOSFET.์ดˆ๊ณ ๋ฐ€๋„ ์ง‘์ ํšŒ๋กœ ๊ธฐ์ˆ ์˜ ๋ฐœ์ „์€ ๊ณ ์ง‘์ ๋„ ๋‹ฌ์„ฑ์„ ํ†ตํ•ด ๋‹จ์œ„ ์นฉ์˜ ์—ฐ์‚ฐ ์†๋„ ๋ฐ ์šฉ๋Ÿ‰ ํ–ฅ์ƒ์— ๊ธฐ์—ฌํ•  ์†Œํ˜•์˜ ์†Œ์ž๋ฅผ ๋Š์ž„์—†์ด ์š”๊ตฌํ•˜๊ณ  ์žˆ๋‹ค. ํ•˜์ง€๋งŒ ์ตœ์‹ ์˜ ์ƒ๋ณดํ˜• ๊ธˆ์†-์‚ฐํ™”๋ง‰-๋ฐ˜๋„์ฒด (CMOS) ๊ธฐ์ˆ ์—์„œ ๊ธˆ์†-์‚ฐํ™”๋ง‰-๋ฐ˜๋„์ฒด ์ „๊ณ„ ํšจ๊ณผ ํŠธ๋žœ์ง€์Šคํ„ฐ (MOSFET) ์˜ ๋‹จ์ˆœํ•œ ์†Œํ˜•ํ™”๋Š” ๋” ์ด์ƒ ์ง‘์ ํšŒ๋กœ์˜ ์„ฑ๋Šฅ ํ–ฅ์ƒ์„ ๋ณด์žฅํ•ด ์ฃผ์ง€ ๋ชปํ•˜๊ณ  ์žˆ๋‹ค. ํŠนํžˆ ์†Œ์ž์˜ ํฌ๊ธฐ๊ฐ€ ์ค„์–ด๋“œ๋Š” ๋ฐ˜๋ฉด ์ •์  ์ „๋ ฅ ์†Œ๋ชจ๋Ÿ‰์€ ์ „์•• ์Šค์ผ€์ผ๋ง์˜ ๋‘”ํ™”๋กœ ์ธํ•ด ๊ฐ์†Œ๋˜์ง€ ์•Š๊ณ  ์žˆ๋Š” ์ƒํ™ฉ์ด๋‹ค. MOSFET์˜ ์งง์€ ์ฑ„๋„ ํšจ๊ณผ๋กœ ์ธํ•ด ์ฆ๊ฐ€๋œ ๋ˆ„์„ค ์ „๋ฅ˜๊ฐ€ ์ „์•• ์Šค์ผ€์ผ๋ง์˜ ์–ด๋ ค์›€์„ ์ฃผ๋Š” ๋Œ€ํ‘œ์  ์›์ธ์œผ๋กœ ๊ผฝํžŒ๋‹ค. ์ด๋Ÿฌํ•œ ๊ทผ๋ณธ์ ์ธ MOSFET์˜ ํ•œ๊ณ„๋ฅผ ๊ทน๋ณตํ•˜๊ธฐ ์œ„ํ•˜์—ฌ ์ง€๋‚œ 10์—ฌ๋…„๊ฐ„ ์ƒˆ๋กœ์šด ๋‹จ๊ณ„์˜ ์ „๊ณ„ ํšจ๊ณผ ํŠธ๋žœ์ง€์Šคํ„ฐ ์†Œ์ž๋“ค์ด ์—ฐ๊ตฌ๋˜๊ณ  ์žˆ๋‹ค. ๊ทธ ์ค‘ ํ„ฐ๋„ ์ „๊ณ„ ํšจ๊ณผ ํŠธ๋žœ์ง€์Šคํ„ฐ(TFET)์€ ๊ทธ ํŠน์œ ์˜ ์šฐ์ˆ˜ํ•œ ์ „์› ํŠน์„ฑ์œผ๋กœ ๊ฐ๊ด‘๋ฐ›์•„ ์ง‘์ค‘์ ์œผ๋กœ ์—ฐ๊ตฌ๋˜๊ณ  ์žˆ๋‹ค. ๋งŽ์€ ์—ฐ๊ตฌ์—๋„ ๋ถˆ๊ตฌํ•˜๊ณ , TFET์˜ ๋ถ€์กฑํ•œ ์ „๋ฅ˜ ๊ตฌ๋™ ๋Šฅ๋ ฅ์€ MOSFET์˜ ๋Œ€์ฒด์žฌ๋กœ ์ž๋ฆฌ๋งค๊น€ํ•˜๋Š” ๋ฐ ๊ฐ€์žฅ ํฐ ๋ฌธ์ œ์ ์ด ๋˜๊ณ  ์žˆ๋‹ค. ๋ณธ ํ•™์œ„๋…ผ๋ฌธ์—์„œ๋Š” ์ƒ๊ธฐ๋œ ๋ฌธ์ œ์ ์„ ํ•ด๊ฒฐํ•  ์ˆ˜ ์žˆ๋Š” ์šฐ์ˆ˜ํ•œ ์ „๋ฅ˜ ๊ตฌ๋™ ๋Šฅ๋ ฅ์„ ๊ฐ€์ง„ TFET์ด ์ œ์•ˆ๋˜์—ˆ๋‹ค. ๋ฐ˜์†ก์ž ์œ ์ž…๊ณผ ๊ฒŒ์ดํŠธ ์ปจํŠธ๋กค์„ ํ–ฅ์ƒ์‹œํ‚ฌ ์ˆ˜ ์žˆ๋Š” ์ˆ˜์ง ์ ์ธต๋œ ์‹ค๋ฆฌ์ฝ˜์ €๋งˆ๋Š„(SiGe) ๋‚˜๋…ธ์‹œํŠธ ์ฑ„๋„์ด ์‚ฌ์šฉ๋˜์—ˆ๋‹ค. ๋˜ํ•œ, ์ œ์•ˆ๋œ TFET์€ CMOS ๊ธฐ๋ฐ˜ ๊ณต์ •์„ ํ™œ์šฉํ•˜์—ฌ MOSFET๊ณผ ํ•จ๊ป˜ ์ œ์ž‘๋˜์—ˆ๋‹ค. ํ…Œํฌ๋†€๋กœ์ง€ ์ปดํ“จํ„ฐ ์ง€์› ์„ค๊ณ„(TCAD) ์‹œ๋ฎฌ๋ ˆ์ด์…˜๊ณผ ์‹ค์ œ ์ธก์ • ๊ฒฐ๊ณผ๋ฅผ ํ™œ์šฉํ•˜์—ฌ ์ œ์•ˆ๋œ ์†Œ์ž์˜ ์šฐ์ˆ˜์„ฑ์„ ๊ฒ€์ฆํ•˜์˜€๋‹ค. ๋‹จ์œ„ CMOS ์†Œ์ž์˜ ๊ด€์ ์—์„œ, ์ „์› ํŠน์„ฑ๊ณผ ์ „๋ฅ˜ ๊ตฌ๋™ ๋Šฅ๋ ฅ์˜ ํ–ฅ์ƒ์„ ์ •๋Ÿ‰์ , ์ •์„ฑ์  ๋ฐฉ๋ฒ•์œผ๋กœ ๋ถ„์„ํ•˜์˜€๋‹ค. ๊ทธ๋ฆฌ๊ณ , ์ œ์ž‘๋œ ์†Œ์ž์˜ ์„ฑ๋Šฅ์„ ๊ธฐ์กด ์ œ์ž‘ ๋ฐ ๋ณด๊ณ ๋œ TFET ๋ฐ ํ•จ๊ป˜ ์ œ์ž‘๋œ MOSSFET๊ณผ ๋น„๊ตํ•˜์˜€๋‹ค. ์ด๋Ÿฌํ•œ ๊ณผ์ •์„ ํ†ตํ•ด, ์‹ค๋ฆฌ์ฝ˜์ €๋งˆ๋Š„ ๋‚˜๋…ธ์‹œํŠธ TFET์˜ ํ™œ์šฉ ๊ฐ€๋Šฅ์„ฑ์ด ์ž…์ฆ๋˜์—ˆ๋‹ค. ์ œ์•ˆ๋œ ์‹ค๋ฆฌ์ฝ˜์ €๋งˆ๋Š„ ๋‚˜๋…ธ์‹œํŠธ ์†Œ์ž๋Š” ์ฃผ๋ชฉํ•  ๋งŒํ•œ ์ „์› ํŠน์„ฑ์„ ๊ฐ€์กŒ๊ณ  ์ €์ „์•• ๊ตฌ๋™ ํ™˜๊ฒฝ์—์„œ ํ•œ์ธต ๋” ๋‚ฎ์€ ๋ˆ„์„ค ์ „๋ฅ˜๋ฅผ ๊ฐ€์ง์œผ๋กœ์จ ํ–ฅํ›„ MOSFET์„ ๋Œ€์ฒดํ• ๋งŒํ•œ ์ถฉ๋ถ„ํ•œ ๊ฐ€๋Šฅ์„ฑ์„ ๋ณด์—ฌ์ฃผ์—ˆ๋‹ค.Chapter 1 Introduction 1 1.1. Power Crisis of Conventional CMOS Technology 1 1.2. Tunnel Field-Effect Transistor (TFET) 6 1.3. Feasibility and Challenges of TFET 9 1.4. Scope of Thesis 11 Chapter 2 Device Characterization 13 2.1. SiGe Nanosheet TFET 13 2.2. Device Concept 15 2.3. Calibration Procedure for TCAD simulation 17 2.4. Device Verification with TCAD simulation 21 Chapter 3 Device Fabrication 31 3.1. Fabrication Process Flow 31 3.2. Key Processes for SiGe Nanosheet TFET 33 3.2.1. Key Process 1 : SiGe Nanosheet Formation 34 3.2.2. Key Process 2 : Source/Drain Implantation 41 3.2.3. Key Process 3 : High-ฮบ/Metal gate Formation 43 Chapter 4 Results and Discussion 53 4.1. Measurement Results 53 4.2. Analysis of Device Characteristics 56 4.2.1. Improved Factors to Performance in SiGe Nanosheet TFET 56 4.2.2. Performance Comparison with SiGe Nanosheet MOSFET 62 4.3. Performance Evaluation through Benchmarks 64 4.4. Optimization Plan for SiGe nanosheet TFET 66 4.4.1. Improvement of Quality of Gate Dielectric 66 4.4.2. Optimization of Doping Junction at Source 67 Chapter 5 Conclusion 71 Bibliography 73 Abstract in Korean 81 List of Publications 83Docto

    Quantum and spin-based tunneling devices for memory systems

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    Rapid developments in information technology, such as internet, portable computing, and wireless communication, create a huge demand for fast and reliable ways to store and process information. Thus far, this need has been paralleled with the revolution in solid-state memory technologies. Memory devices, such as SRAM, DRAM, and flash, have been widely used in most electronic products. The primary strategy to keep up the trend is miniaturization. CMOS devices have been scaled down beyond sub-45 nm, the size of only a few atomic layers. Scaling, however, will soon reach the physical limitation of the material and cease to yield the desired enhancement in device performance. In this thesis, an alternative method to scaling is proposed and successfully realized. The proposed scheme integrates quantum devices, Si/SiGe resonant interband tunnel diodes (RITD), with classical CMOS devices forming a microsystem of disparate devices to achieve higher performance as well as higher density. The device/circuit designs, layouts and masks involving 12 levels were fabricated utilizing a process that incorporates nearly a hundred processing steps. Utilizing unique characteristics of each component, a low-power tunneling-based static random access memory (TSRAM) has been demonstrated. The TSRAM cells exhibit bistability operation with a power supply voltage as low as 0.37 V. Various TSRAM cells were also constructed and their latching mechanisms have been extensively investigated. In addition, the operation margins of TSRAM cells are evaluated based on different device structures and temperature variation from room temperature up to 200oC. The versatility of TSRAM is extended beyond the binary system. Using multi-peak Si/SiGe RITD, various multi-valued TSRAM (MV-TSRAM) configurations that can store more than two logic levels per cell are demonstrated. By this virtue, memory density can be substantially increased. Using two novel methods via ambipolar operation and utilization of enable/disable transistors, a six-valued MV-TSRAM cell are demonstrated. A revolutionary novel concept of integrating of Si/SiGe RITD with spin tunnel devices, magnetic tunnel junctions (MTJ), has been developed. This hybrid approach adds non-volatility and multi-valued memory potential as demonstrated by theoretical predictions and simulations. The challenges of physically fabricating these devices have been identified. These include process compatibility and device design. A test bed approach of fabricating RITD-MTJ structures has been developed. In conclusion, this body of work has created a sound foundation for new research frontiers in four different major areas: integrated TSRAM system, MV-TSRAM system, MTJ/RITD-based nonvolatile MRAM, and RITD/CMOS logic circuits

    Dielectric-Modulated TFETs as Label-Free Biosensors

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    This chapter presents tunnel field effect transistors (TFETs) as dielectric-modulated (DM) label-free biosensors, and discusses various aspects related to them. A brief survey of the dielectric-modulated TFET biosensors is presented. The concept of dielectric modulation in TFETs is discussed with focus on principle and design perspectives. A Technology Computer Aided Design (TCAD) based approach to incorporate embedded nanogaps in TFET geometries along with appropriate physics-based simulation models are mentioned. Non-ideal conditions in dielectric-modulated biosensors are brought to light, keeping in view the practical considerations of the devices. A gate engineered TFET is taken up for analysis of sensitivities under different conditions through TCAD simulations. Finally, a status map of the sensitivities of the most significant works in dielectric-modulated label-free biosensors is depicted, and the status of the proposed TFET is highlighted

    Miniaturized Transistors

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    What is the future of CMOS? Sustaining increased transistor densities along the path of Moore's Law has become increasingly challenging with limited power budgets, interconnect bandwidths, and fabrication capabilities. In the last decade alone, transistors have undergone significant design makeovers; from planar transistors of ten years ago, technological advancements have accelerated to today's FinFETs, which hardly resemble their bulky ancestors. FinFETs could potentially take us to the 5-nm node, but what comes after it? From gate-all-around devices to single electron transistors and two-dimensional semiconductors, a torrent of research is being carried out in order to design the next transistor generation, engineer the optimal materials, improve the fabrication technology, and properly model future devices. We invite insight from investigators and scientists in the field to showcase their work in this Special Issue with research papers, short communications, and review articles that focus on trends in micro- and nanotechnology from fundamental research to applications

    Improving the Readout of Semiconducting Qubits

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    Semiconducting qubits are a promising platform for quantum computers. In particular, silicon spin qubits have made a number of advancements recently including long coherence times, high-fidelity single-qubit gates, two-qubit gates, and high-fidelity readout. However, all operations likely require improvement in fidelity and speed, if possible, to realize a quantum computer. Readout fidelity and speed, in general, are limited by circuit challenges centered on extracting low signal from a device in a dilution refrigerator connected to room temperature amplifiers by long coaxial cables with relatively high capacitance. Readout fidelity specifically is limited by the time it takes to reliably distinguish qubit states relative to the characteristic decay time of the excited state, T1. This dissertation explores the use of heterojunction bipolar transistor (HBT) circuits to amplify the readout signal of silicon spin qubits at cryogenic temperatures. The cryogenic amplification approach has numerous advantages including low implementation overhead, low power relative to the available cooling power, and high signal gain at the mixing chamber stage leading to around a factor of ten speedup in readout time for a similar signal-to-noise ratio. The faster readout time generally increases fidelity, since it is much faster than the T1 time. Two HBT amplification circuits have been designed and characterized. One design is a low-power, base-current biased configuration with non-linear gain (CB-HBT), and the second is a linear-gain, AC-coupled configuration (AC-HBT). They can operate at powers of 1 and 10 ฮผW, respectfully, and not significantly heat electrons. The noise spectral density referred to the input for both circuits is around 15 to 30 fA/โˆšHz, which is low compared to previous cases such as the dual-stage, AC-coupled HEMT circuit at ~ 70 fA/โˆšHz. Both circuits achieve charge sensitivity between 300 and 400 ฮผe/โˆšHz, which approaches the best alternatives (e.g., RF-SET at ~ 140 ฮผe/โˆšHz) but with much less implementation overhead. For the single-shot latched charge readout performed, both circuits achieve high-fidelity readout in times \u3c 10 ฮผs with bit error rates \u3c 10-3, which is a great improvement over previous work at \u3e 70 ฮผs. The readout speed-up in principle also reduces the production of errors due to excited state relaxation by a factor of ~ 10. All of these results are possible with relatively simple, low-power transistor circuits which can be mounted close to the qubit device at the mixing chamber stage of the dilution refrigerator

    Resonant tunnelling features in the transport spectroscopy of quantum dots

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    We present a review of features due to resonant tunnelling in transport spectroscopy experiments on quantum dots and single donors. The review covers features attributable to intrinsic properties of the dot as well as extrinsic effects, with a focus on the most common operating conditions. We describe several phenomena that can lead to apparently identical signatures in a bias spectroscopy measurement, with the aim of providing experimental methods to distinguish between their different physical origins. The correct classification of the resonant tunnelling features is an essential requirement to understand the details of the confining potential or predict the performance of the dot for quantum information processing.Comment: 18 pages, 7 figures. Short review article submitted to Nanotechnology, special issue on 'Quantum Science and Technology at the Nanoscale

    Concept, design, simulation, and fabrication of an ultra-scalable vertical MOSFET

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    A new orientation to the conventional MOSFET is proposed. Processing issues, as well as short channel effects have been making planar MOSFET scaling increasingly difficult. It is predicted by the 2001 International Technology Roadmap for Semiconductors (ITRS) that non-planar devices will be needed for production as early as 2007. The device proposed in this thesis is similar in operation to the planar MOSFET, however the current transport from source to drain, normally in the same plane as the wafer surface, is oriented perpendicular to the die surface. The proposed device has successfully been simulated, showing a proof of concept. Fabrication of the proposed devices led to the creation of vertical MOS Gated Tunnel Diodes. This work, in fact, represents possibly the first demonstration of this type of technology. Suggestions are made to improve upon the proposed vertical MOSFET as well as the vertical MOS Gated Tunnel Diode
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