높은 전류 구동능력을 가지는 SiGe 나노시트 구조의 터널링 전계효과 트랜지스터

학위논문 (박사) -- 서울대학교 대학원 : 공과대학 전기·정보공학부, 2021. 2. 박병국.The development of very-large-scale integration (VLSI) technology has continuously demanded smaller devices to achieve high integration density for faster computing speed or higher capacity. However, in the recent complementary-metal-oxide-semiconductor (CMOS) technology, simple downsizing the dimension of metal-oxide-semiconductor field-effect transistor (MOSFET) no longer guarantees the boosting performance of IC chips. In particular, static power consumption is not reduced while device size is decreasing because voltage scaling is slowed down at some point. The increased off-current due to short-channel effect (SCE) of MOSFET is a representative cause of the difficulty in voltage scaling. To overcome these fundamental limits of MOSFET, many researchers have been looking for the next generation of FET device over the last ten years. Tunnel field-effect transistor (TFET) has been intensively studied for its steep switching characteristics. Nevertheless, the poor current drivability of TFET is the most serious obstacle to become competitive device for MOSFET. In this thesis, TFET with high current drivability in which above-mentioned problem is significantly solved is proposed. Vertically-stacked SiGe nanosheet channels are used to boost carrier injection and gate control. The fabrication technique to form highly-condensed SiGe nanosheets is introduced. TFET is fabricated with MOSFET with the same structure in the CMOS-compatible process. Both technology-computer-aided-design (TCAD) simulation and experimental results are utilized to support and examine the advantages of proposed TFET. From the perspective of the single device, the improvement in switching characteristics and current drivability are quantitatively and qualitatively analyzed. In addition, the device performance is compared to the benchmark of previously reported TFET and co-fabricated MOSFET. Through those processes, the feasibility of SiGe nanosheet TFET is verified. It is revealed that the proposed SiGe nanosheet TFET has notable steeper switching and low leakage in the low drive voltage as an alternative to conventional MOSFET.초고밀도 집적회로 기술의 발전은 고집적도 달성을 통해 단위 칩의 연산 속도 및 용량 향상에 기여할 소형의 소자를 끊임없이 요구하고 있다. 하지만 최신의 상보형 금속-산화막-반도체 (CMOS) 기술에서 금속-산화막-반도체 전계 효과 트랜지스터 (MOSFET) 의 단순한 소형화는 더 이상 집적회로의 성능 향상을 보장해 주지 못하고 있다. 특히 소자의 크기가 줄어드는 반면 정적 전력 소모량은 전압 스케일링의 둔화로 인해 감소되지 않고 있는 상황이다. MOSFET의 짧은 채널 효과로 인해 증가된 누설 전류가 전압 스케일링의 어려움을 주는 대표적 원인으로 꼽힌다. 이러한 근본적인 MOSFET의 한계를 극복하기 위하여 지난 10여년간 새로운 단계의 전계 효과 트랜지스터 소자들이 연구되고 있다. 그 중 터널 전계 효과 트랜지스터(TFET)은 그 특유의 우수한 전원 특성으로 각광받아 집중적으로 연구되고 있다. 많은 연구에도 불구하고, TFET의 부족한 전류 구동 능력은 MOSFET의 대체재로 자리매김하는 데 가장 큰 문제점이 되고 있다. 본 학위논문에서는 상기된 문제점을 해결할 수 있는 우수한 전류 구동 능력을 가진 TFET이 제안되었다. 반송자 유입과 게이트 컨트롤을 향상시킬 수 있는 수직 적층된 실리콘저마늄(SiGe) 나노시트 채널이 사용되었다. 또한, 제안된 TFET은 CMOS 기반 공정을 활용하여 MOSFET과 함께 제작되었다. 테크놀로지 컴퓨터 지원 설계(TCAD) 시뮬레이션과 실제 측정 결과를 활용하여 제안된 소자의 우수성을 검증하였다. 단위 CMOS 소자의 관점에서, 전원 특성과 전류 구동 능력의 향상을 정량적, 정성적 방법으로 분석하였다. 그리고, 제작된 소자의 성능을 기존 제작 및 보고된 TFET 및 함께 제작된 MOSSFET과 비교하였다. 이러한 과정을 통해, 실리콘저마늄 나노시트 TFET의 활용 가능성이 입증되었다. 제안된 실리콘저마늄 나노시트 소자는 주목할 만한 전원 특성을 가졌고 저전압 구동 환경에서 한층 더 낮은 누설 전류를 가짐으로써 향후 MOSFET을 대체할만한 충분한 가능성을 보여주었다.Chapter 1 Introduction 1 1.1. Power Crisis of Conventional CMOS Technology 1 1.2. Tunnel Field-Effect Transistor (TFET) 6 1.3. Feasibility and Challenges of TFET 9 1.4. Scope of Thesis 11 Chapter 2 Device Characterization 13 2.1. SiGe Nanosheet TFET 13 2.2. Device Concept 15 2.3. Calibration Procedure for TCAD simulation 17 2.4. Device Verification with TCAD simulation 21 Chapter 3 Device Fabrication 31 3.1. Fabrication Process Flow 31 3.2. Key Processes for SiGe Nanosheet TFET 33 3.2.1. Key Process 1 : SiGe Nanosheet Formation 34 3.2.2. Key Process 2 : Source/Drain Implantation 41 3.2.3. Key Process 3 : High-κ/Metal gate Formation 43 Chapter 4 Results and Discussion 53 4.1. Measurement Results 53 4.2. Analysis of Device Characteristics 56 4.2.1. Improved Factors to Performance in SiGe Nanosheet TFET 56 4.2.2. Performance Comparison with SiGe Nanosheet MOSFET 62 4.3. Performance Evaluation through Benchmarks 64 4.4. Optimization Plan for SiGe nanosheet TFET 66 4.4.1. Improvement of Quality of Gate Dielectric 66 4.4.2. Optimization of Doping Junction at Source 67 Chapter 5 Conclusion 71 Bibliography 73 Abstract in Korean 81 List of Publications 83Docto

Quantum and spin-based tunneling devices for memory systems

Rapid developments in information technology, such as internet, portable computing, and wireless communication, create a huge demand for fast and reliable ways to store and process information. Thus far, this need has been paralleled with the revolution in solid-state memory technologies. Memory devices, such as SRAM, DRAM, and flash, have been widely used in most electronic products. The primary strategy to keep up the trend is miniaturization. CMOS devices have been scaled down beyond sub-45 nm, the size of only a few atomic layers. Scaling, however, will soon reach the physical limitation of the material and cease to yield the desired enhancement in device performance. In this thesis, an alternative method to scaling is proposed and successfully realized. The proposed scheme integrates quantum devices, Si/SiGe resonant interband tunnel diodes (RITD), with classical CMOS devices forming a microsystem of disparate devices to achieve higher performance as well as higher density. The device/circuit designs, layouts and masks involving 12 levels were fabricated utilizing a process that incorporates nearly a hundred processing steps. Utilizing unique characteristics of each component, a low-power tunneling-based static random access memory (TSRAM) has been demonstrated. The TSRAM cells exhibit bistability operation with a power supply voltage as low as 0.37 V. Various TSRAM cells were also constructed and their latching mechanisms have been extensively investigated. In addition, the operation margins of TSRAM cells are evaluated based on different device structures and temperature variation from room temperature up to 200oC. The versatility of TSRAM is extended beyond the binary system. Using multi-peak Si/SiGe RITD, various multi-valued TSRAM (MV-TSRAM) configurations that can store more than two logic levels per cell are demonstrated. By this virtue, memory density can be substantially increased. Using two novel methods via ambipolar operation and utilization of enable/disable transistors, a six-valued MV-TSRAM cell are demonstrated. A revolutionary novel concept of integrating of Si/SiGe RITD with spin tunnel devices, magnetic tunnel junctions (MTJ), has been developed. This hybrid approach adds non-volatility and multi-valued memory potential as demonstrated by theoretical predictions and simulations. The challenges of physically fabricating these devices have been identified. These include process compatibility and device design. A test bed approach of fabricating RITD-MTJ structures has been developed. In conclusion, this body of work has created a sound foundation for new research frontiers in four different major areas: integrated TSRAM system, MV-TSRAM system, MTJ/RITD-based nonvolatile MRAM, and RITD/CMOS logic circuits

Dielectric-Modulated TFETs as Label-Free Biosensors

This chapter presents tunnel field effect transistors (TFETs) as dielectric-modulated (DM) label-free biosensors, and discusses various aspects related to them. A brief survey of the dielectric-modulated TFET biosensors is presented. The concept of dielectric modulation in TFETs is discussed with focus on principle and design perspectives. A Technology Computer Aided Design (TCAD) based approach to incorporate embedded nanogaps in TFET geometries along with appropriate physics-based simulation models are mentioned. Non-ideal conditions in dielectric-modulated biosensors are brought to light, keeping in view the practical considerations of the devices. A gate engineered TFET is taken up for analysis of sensitivities under different conditions through TCAD simulations. Finally, a status map of the sensitivities of the most significant works in dielectric-modulated label-free biosensors is depicted, and the status of the proposed TFET is highlighted

Miniaturized Transistors

What is the future of CMOS? Sustaining increased transistor densities along the path of Moore's Law has become increasingly challenging with limited power budgets, interconnect bandwidths, and fabrication capabilities. In the last decade alone, transistors have undergone significant design makeovers; from planar transistors of ten years ago, technological advancements have accelerated to today's FinFETs, which hardly resemble their bulky ancestors. FinFETs could potentially take us to the 5-nm node, but what comes after it? From gate-all-around devices to single electron transistors and two-dimensional semiconductors, a torrent of research is being carried out in order to design the next transistor generation, engineer the optimal materials, improve the fabrication technology, and properly model future devices. We invite insight from investigators and scientists in the field to showcase their work in this Special Issue with research papers, short communications, and review articles that focus on trends in micro- and nanotechnology from fundamental research to applications

Improving the Readout of Semiconducting Qubits

Semiconducting qubits are a promising platform for quantum computers. In particular, silicon spin qubits have made a number of advancements recently including long coherence times, high-fidelity single-qubit gates, two-qubit gates, and high-fidelity readout. However, all operations likely require improvement in fidelity and speed, if possible, to realize a quantum computer. Readout fidelity and speed, in general, are limited by circuit challenges centered on extracting low signal from a device in a dilution refrigerator connected to room temperature amplifiers by long coaxial cables with relatively high capacitance. Readout fidelity specifically is limited by the time it takes to reliably distinguish qubit states relative to the characteristic decay time of the excited state, T1. This dissertation explores the use of heterojunction bipolar transistor (HBT) circuits to amplify the readout signal of silicon spin qubits at cryogenic temperatures. The cryogenic amplification approach has numerous advantages including low implementation overhead, low power relative to the available cooling power, and high signal gain at the mixing chamber stage leading to around a factor of ten speedup in readout time for a similar signal-to-noise ratio. The faster readout time generally increases fidelity, since it is much faster than the T1 time. Two HBT amplification circuits have been designed and characterized. One design is a low-power, base-current biased configuration with non-linear gain (CB-HBT), and the second is a linear-gain, AC-coupled configuration (AC-HBT). They can operate at powers of 1 and 10 μW, respectfully, and not significantly heat electrons. The noise spectral density referred to the input for both circuits is around 15 to 30 fA/√Hz, which is low compared to previous cases such as the dual-stage, AC-coupled HEMT circuit at ~ 70 fA/√Hz. Both circuits achieve charge sensitivity between 300 and 400 μe/√Hz, which approaches the best alternatives (e.g., RF-SET at ~ 140 μe/√Hz) but with much less implementation overhead. For the single-shot latched charge readout performed, both circuits achieve high-fidelity readout in times \u3c 10 μs with bit error rates \u3c 10-3, which is a great improvement over previous work at \u3e 70 μs. The readout speed-up in principle also reduces the production of errors due to excited state relaxation by a factor of ~ 10. All of these results are possible with relatively simple, low-power transistor circuits which can be mounted close to the qubit device at the mixing chamber stage of the dilution refrigerator

Resonant tunnelling features in the transport spectroscopy of quantum dots

We present a review of features due to resonant tunnelling in transport spectroscopy experiments on quantum dots and single donors. The review covers features attributable to intrinsic properties of the dot as well as extrinsic effects, with a focus on the most common operating conditions. We describe several phenomena that can lead to apparently identical signatures in a bias spectroscopy measurement, with the aim of providing experimental methods to distinguish between their different physical origins. The correct classification of the resonant tunnelling features is an essential requirement to understand the details of the confining potential or predict the performance of the dot for quantum information processing.Comment: 18 pages, 7 figures. Short review article submitted to Nanotechnology, special issue on 'Quantum Science and Technology at the Nanoscale

Concept, design, simulation, and fabrication of an ultra-scalable vertical MOSFET

A new orientation to the conventional MOSFET is proposed. Processing issues, as well as short channel effects have been making planar MOSFET scaling increasingly difficult. It is predicted by the 2001 International Technology Roadmap for Semiconductors (ITRS) that non-planar devices will be needed for production as early as 2007. The device proposed in this thesis is similar in operation to the planar MOSFET, however the current transport from source to drain, normally in the same plane as the wafer surface, is oriented perpendicular to the die surface. The proposed device has successfully been simulated, showing a proof of concept. Fabrication of the proposed devices led to the creation of vertical MOS Gated Tunnel Diodes. This work, in fact, represents possibly the first demonstration of this type of technology. Suggestions are made to improve upon the proposed vertical MOSFET as well as the vertical MOS Gated Tunnel Diode