Statistical Yield Modeling for IC Manufacture: Hierarchical Fault Distributions

A hierarchical approach to the construction of compound distributions for process-induced faults in IC manufacture is proposed. Within this framework, the negative binomial distribution and the compound binomial distribution are treated as level-1 models. The hierarchical approach to fault distribution offers an integrated picture of how fault density varies from region to region within a wafer, from wafer to wafer within a batch, and so on. A theory of compound-distribution hierarchies is developed by means of generating functions. With respect to applications, hierarchies of yield means and yield probability-density functions are considered and an in-process measure of yield loss is introduced. It is shown that the hierarchical approach naturally embraces the Bayesian approach.Comment: OAO Angstrem, Moscow Institute of Electronic Engineering (Technical University), Moscow, Russia, 19 pages, 2 figure

Should Yield be a Design Objective?

The objectives of good chip design have traditionally included issues like performance, power and reliability. Yield is rarely considered during the design process, except in the design of memory ICs, where specic defect-tolerance techniques are incorporated into the architecture for yield enhancement. In order to make the case for establishing yield as another design objective we must rst prove that a chip's yield can not only be aected, but consistently improved, by decisions made during the design process. 1