Shared Memory Implementation of A Parallel Switch-Level Circuit Simulator

Circuit simulation is a critical bottleneck in VLSI design. This paper describes the implementation of an existing parallel switch-level simulator called MIRSIM on a shared-memory multiprocessor architecture. The simulator uses a set of three different conservative protocols: the null message protocol, the conditional event protocol and the accelerated null message protocol, a combinations of the preceding two algorithms. The paper describes the implementation of these protocols to exploit shared-memory features, measures their relative performance for a set of six benchmark circuits ranging in size from 3000 to almost 70,000 transistors, and compares the speedup obtained by each of the three protocols. 1 Introduction A number of factors govern the performance of parallel circuit simulation [5]: circuit characteristics that determine the inherent parallelism in the design; the timing models and abstraction level used by the simulators; the partitioning methods used to decompose the c..