A feasibility study on the use of arithmetic-memory registers in the design of digital computer systems

The concept of combining arithmetic and memory capability on a single semiconductor chip has become practical from a system's viewpoint through the decreased cost of semiconductor memories and high circuit densities achieved through large scale integration. This paper describes a model for studying the feasibility of such systems. An arithmetic-memory register is defined as the basic hardware unit. A model consisting of instruction states and transition states is developed. The model is then applied to both past and contemporary computer structures. A general purpose machine is formulated from a set of arithmetic-memory registers. The feasibility of this structure is studied with respect to both performance and implementation. The utilization of arithmetic-memory registers is also shown to be applicable to special-purpose systems. A system designed to compute power spectra is described. The state model proved to be a useful technique in the design of the system. Cost estimates and measures of performance were significant factors influencing the feasibility of the system. The structure was also found suitable for real-time application

System design of a hardware Fortran compiler

This paper describes the system design of a Fortran hardware compiler which converts the original code of a source program into an intermediate code. This code contains features that allow easy machine code generation. An evaluation is first made on the marketability of such a system and then a brief discussion on the features of the intermediate code generated by the hardware compiler. The system is divided into a number of functional blocks. Each block consists of a control unit and a set of hardware logic components. The control unit is realized by Programmable Logic Arrays and all hardware components are state-of-the-art products. Estimates on the typical operating speeds of the functional blocks are made. Flow charts and state diagrams are used to describe the logic flow of the functional blocks