Self-Timed Divider Based on RSD Number System

This paper proposes a divider structure that combines a novel self-timed ring structure and a carry-propagation-free division algorithm. The self-timed ring structure enables the divider to compute at a speed comparable to that of previously designed dividers with less silicon area. By exploiting the carry-propagation-free division algorithm, we can achieve even better performance. We designed a layout of 54-bit divider using 1.2¯m CMOS technology and measured the area and speed. We obtained a speed of 135 ns per worst case division on 5.7 mm 2 of silicon area. I. Introduction There are two commonly used approaches to implementing a hardware divider --- sequential and combinational[1], [2]. In general, the sequential approach requires less silicon area at the expense of slow operation and possible performance limitations caused by employing a clock. A totally combinational array is faster but at the expense of large silicon area. The structure of the divider proposed in this paper a..