Self-IQ-Demodulation Based Compensation Scheme of Frequency-Dependent IQ Imbalance for Wideband Direct-Conversion Transmitters

A low cost frequency-dependent (FD) I/Q imbalance self-compensation scheme is investigated in this paper. The direct conversion transmitters are widely used in wireless systems. However, the unwanted image-frequencies and distortions are inevitably introduced into the direct conversion system. This problem is even severer in wideband systems. Therefore, the accurate estimation and compensation of I/Q imbalance is crucial. The current compensation method is based on external instruments or internal feedback path which introduces additional impairments and is expensive. This paper proposes a low cost FD I/Q imbalance self-IQ-demodulation based compensation scheme without using external calibration instruments. First, the impairments of baseband and RF components are investigated. Further, I/Q imbalance model is developed. Then, the proposed two-step self-IQ-demodulation based compensation scheme is investigated. In the first step of the scheme, the local oscillator (LO) related I/Q impairments parameters are estimated. Then in the second step, the overall FD I/Q imbalance parameters are estimated by utilizing the transmitter LO. To realize this self-IQ-demodulation algorithm, this paper introduces minor modifications to the current power detector circuit. Afterwards, the estimated parameters are applied to the baseband equivalent compensator. This sophisticated algorithm guarantees low computation complexity and low cost. The compensation performance is evaluated in laboratory measurement

System capacity enhancement for 5G network and beyond

A thesis submitted to the University of Bedfordshire, in fulfilment of the requirements for the degree of Doctor of PhilosophyThe demand for wireless digital data is dramatically increasing year over year. Wireless communication systems like Laptops, Smart phones, Tablets, Smart watch, Virtual Reality devices and so on are becoming an important part of people’s daily life. The number of mobile devices is increasing at a very fast speed as well as the requirements for mobile devices such as super high-resolution image/video, fast download speed, very short latency and high reliability, which raise challenges to the existing wireless communication networks. Unlike the previous four generation communication networks, the fifth-generation (5G) wireless communication network includes many technologies such as millimetre-wave communication, massive multiple-input multiple-output (MIMO), visual light communication (VLC), heterogeneous network (HetNet) and so forth. Although 5G has not been standardised yet, these above technologies have been studied in both academia and industry and the goal of the research is to enhance and improve the system capacity for 5G networks and beyond by studying some key problems and providing some effective solutions existing in the above technologies from system implementation and hardware impairments’ perspective. The key problems studied in this thesis include interference cancellation in HetNet, impairments calibration for massive MIMO, channel state estimation for VLC, and low latency parallel Turbo decoding technique. Firstly, inter-cell interference in HetNet is studied and a cell specific reference signal (CRS) interference cancellation method is proposed to mitigate the performance degrade in enhanced inter-cell interference coordination (eICIC). This method takes carrier frequency offset (CFO) and timing offset (TO) of the user’s received signal into account. By reconstructing the interfering signal and cancelling it afterwards, the capacity of HetNet is enhanced. Secondly, for massive MIMO systems, the radio frequency (RF) impairments of the hardware will degrade the beamforming performance. When operated in time duplex division (TDD) mode, a massive MIMO system relies on the reciprocity of the channel which can be broken by the transmitter and receiver RF impairments. Impairments calibration has been studied and a closed-loop reciprocity calibration method is proposed in this thesis. A test device (TD) is introduced in this calibration method that can estimate the transmitters’ impairments over-the-air and feed the results back to the base station via the Internet. The uplink pilots sent by the TD can assist the BS receivers’ impairment estimation. With both the uplink and downlink impairments estimates, the reciprocity calibration coefficients can be obtained. By computer simulation and lab experiment, the performance of the proposed method is evaluated. Channel coding is an essential part of a wireless communication system which helps fight with noise and get correct information delivery. Turbo codes is one of the most reliable codes that has been used in many standards such as WiMAX and LTE. However, the decoding process of turbo codes is time-consuming and the decoding latency should be improved to meet the requirement of the future network. A reverse interleave address generator is proposed that can reduce the decoding time and a low latency parallel turbo decoder has been implemented on a FPGA platform. The simulation and experiment results prove the effectiveness of the address generator and show that there is a trade-off between latency and throughput with a limited hardware resource. Apart from the above contributions, this thesis also investigated multi-user precoding for MIMO VLC systems. As a green and secure technology, VLC is achieving more and more attention and could become a part of 5G network especially for indoor communication. For indoor scenario, the MIMO VLC channel could be easily ill-conditioned. Hence, it is important to study the impact of the channel state to the precoding performance. A channel state estimation method is proposed based on the signal to interference noise ratio (SINR) of the users’ received signal. Simulation results show that it can enhance the capacity of the indoor MIMO VLC system

Design and Implementation of a Re-Configurable Arbitrary Signal Generator and Radio Frequency Spectrum Analyser

This research is focused on the design, simulation and implementation of a reconfigurable arbitrary signal generator and the design, simulation and implementation of a radio frequency spectrum analyser based on digital signal processing. Until recently, Application Specific Integrated Circuits (ASICs) were used to produce high performance re-configurable function and arbitrary waveform generators with comprehensive modulation capabilities. However, that situation is now changing with the availability of advanced but low cost Field Programmable Gate Arrays (FPGAs), which could be used as an alternative to ASICs in these applications. The availability of high performance FPGA families opens up the opportunity to compete with ASIC solutions at a fraction of the development cost of an ASIC solution. A fast digital signal processing algorithm for digital waveform generation, using primarily but not limited to Direct Digital Synthesis (DDS) technologies, developed and implemented in a field-configurable logic, with control provided by an embedded microprocessor replacing a high cost ASIC design appeared to be a very attractive concept. This research demonstrates that such a concept is feasible in its entirety. A fully functional, low-complexity, low cost, pulse, Gaussian white noise and DDS based function and arbitrary waveform generator, capable of being amplitude, frequency and phase modulated by an internally generated or external modulating signal was implemented in a low-cost FPGA. The FPGA also included the capabilities to perform pulse width modulation and pulse delay modulation on pulse waveforms. Algorithms to up-convert the sampling rate of the external modulating signal using Cascaded Integrator Comb (CIC) filters and using interpolation method were analysed. Both solutions were implemented to compare their hardware complexities. Analysis of generating noise with user-defined distribution is presented. The ability of triggering the generator by an internally generated or an external event to generate a burst of waveforms where the time between the trigger signal and waveform output is fixed was also implemented in the FPGA. Finally, design of interface to a microprocessor to provide control of the versatile waveform generator was also included in the FPGA. This thesis summarises the literature, design considerations, simulation and implementation of the generator design. The second part of the research is focused on radio frequency spectrum analysis based on digital signal processing. Most existing spectrum analysers are analogue in nature and their complexity increases with frequency. Therefore, the possibility of using digital techniques for spectrum analysis was considered. The aim was to come up with digital system architecture for spectrum analysis and to develop and implement the new approach on a suitable digital platform. This thesis analyses the current literature on shifting algorithms to remove spurious responses and highlights its drawbacks. This thesis also analyses existing literature on quadrature receivers and presents novel adaptation of the existing architectures for application in spectrum analysis. A wide band spectrum analyser receiver with compensation for gain and phase imbalances in the Radio Frequency (RF) input range, as well as compensation for gain and phase imbalances within the Intermediate Frequency (IF) pass band complete with Resolution Band Width (RBW) filtering, Video Band Width (VBW) filtering and amplitude detection was implemented in a low cost FPGA. The ability to extract the modulating signal from a frequency or amplitude modulated RF signal was also implemented. The same family of FPGA used in the generator design was chosen to be the digital platform for this design. This research makes arguments for the new architecture and then summarises the literature, design considerations, simulation and implementation of the new digital algorithm for the radio frequency spectrum analyser