Security evaluation and optimization of the delay-based dual-rail pre-charge logic in presence of early evaluation of data

Delay-based Dual-rail Pre-charge Logic (DDPL) has been introduced for counteracting power analysis attacks. Basically DDPL allows to achieve a constant power consumption for each data transition even in presence of capacitive load mismatches, thanks to an asynchronous two-phases evaluation. Unlikely other secure logic styles, in DDPL the clock frequency does not fix the security level since it depends on the value of the delay Δ between the complementary signals, which can be designed to be lower than 1ns using current CMOS technologies. However no works exist in which the DPA-resistance of DDPL is tested in presence of early evaluation, due to the different arrival times of the signals. The aim of this work is to provide and validate through transistor level simulations a theoretical model of the variations of the delay Δ during the evaluation phase for each possible data configuration in order to assess the effect of the early evaluation in DDPL, and to design early evaluation free DDPL gates. Moreover a case study crypto-core implemented both with basic and optimized DDPL gates has been designed in which a Correlation Frequency Power Analysis (CFPA) attack is mounted so to detect any leakage on simulated current traces