1,291 research outputs found

    Towards a centralized multicore automotive system

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    Today’s automotive systems are inundated with embedded electronics to host chassis, powertrain, infotainment, advanced driver assistance systems, and other modern vehicle functions. As many as 100 embedded microcontrollers execute hundreds of millions of lines of code in a single vehicle. To control the increasing complexity in vehicle electronics and services, automakers are planning to consolidate different on-board automotive functions as software tasks on centralized multicore hardware platforms. However, these vehicle software services have different and contrasting timing, safety, and security requirements. Existing vehicle operating systems are ill-equipped to provide all the required service guarantees on a single machine. A centralized automotive system aims to tackle this by assigning software tasks to multiple criticality domains or levels according to their consequences of failures, or international safety standards like ISO 26262. This research investigates several emerging challenges in time-critical systems for a centralized multicore automotive platform and proposes a novel vehicle operating system framework to address them. This thesis first introduces an integrated vehicle management system (VMS), called DriveOS™, for a PC-class multicore hardware platform. Its separation kernel design enables temporal and spatial isolation among critical and non-critical vehicle services in different domains on the same machine. Time- and safety-critical vehicle functions are implemented in a sandboxed Real-time Operating System (OS) domain, and non-critical software is developed in a sandboxed general-purpose OS (e.g., Linux, Android) domain. To leverage the advantages of model-driven vehicle function development, DriveOS provides a multi-domain application framework in Simulink. This thesis also presents a real-time task pipeline scheduling algorithm in multiprocessors for communication between connected vehicle services with end-to-end guarantees. The benefits and performance of the overall automotive system framework are demonstrated with hardware-in-the-loop testing using real-world applications, car datasets and simulated benchmarks, and with an early-stage deployment in a production-grade luxury electric vehicle

    SCALING UP TASK EXECUTION ON RESOURCE-CONSTRAINED SYSTEMS

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    The ubiquity of executing machine learning tasks on embedded systems with constrained resources has made efficient execution of neural networks on these systems under the CPU, memory, and energy constraints increasingly important. Different from high-end computing systems where resources are abundant and reliable, resource-constrained systems only have limited computational capability, limited memory, and limited energy supply. This dissertation focuses on how to take full advantage of the limited resources of these systems in order to improve task execution efficiency from different aspects of the execution pipeline. While the existing literature primarily aims at solving the problem by shrinking the model size according to the resource constraints, this dissertation aims to improve the execution efficiency for a given set of tasks from the following two aspects. Firstly, we propose SmartON, which is the first batteryless active event detection system that considers both the event arrival pattern as well as the harvested energy to determine when the system should wake up and what the duty cycle should be. Secondly, we propose Antler, which exploits the affinity between all pairs of tasks in a multitask inference system to construct a compact graph representation of the task set for a given overall size budget. To achieve the aforementioned algorithmic proposals, we propose the following hardware solutions. One is a controllable capacitor array that can expand the system’s energy storage on-the-fly. The other is a FRAM array that can accommodate multiple neural networks running on one system.Doctor of Philosoph

    A survey on run-time power monitors at the edge

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    Effectively managing energy and power consumption is crucial to the success of the design of any computing system, helping mitigate the efficiency obstacles given by the downsizing of the systems while also being a valuable step towards achieving green and sustainable computing. The quality of energy and power management is strongly affected by the prompt availability of reliable and accurate information regarding the power consumption for the different parts composing the target monitored system. At the same time, effective energy and power management are even more critical within the field of devices at the edge, which exponentially proliferated within the past decade with the digital revolution brought by the Internet of things. This manuscript aims to provide a comprehensive conceptual framework to classify the different approaches to implementing run-time power monitors for edge devices that appeared in literature, leading the reader toward the solutions that best fit their application needs and the requirements and constraints of their target computing platforms. Run-time power monitors at the edge are analyzed according to both the power modeling and monitoring implementation aspects, identifying specific quality metrics for both in order to create a consistent and detailed taxonomy that encompasses the vast existing literature and provides a sound reference to the interested reader

    Medium Voltage Solid-State Transformer:An IEC60076-3 based design

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    Kraftforsyningsmodul for fjernstyrt undervannsfartøy (ROV).

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    Oppgaven omhandler utvikling av et kraftforsyningssystem for ROV.The assignment concerns development of a power supply system for ROV

    Time-sensitive autonomous architectures

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    Autonomous and software-defined vehicles (ASDVs) feature highly complex systems, coupling safety-critical and non-critical components such as infotainment. These systems require the highest connectivity, both inside the vehicle and with the outside world. An effective solution for network communication lies in Time-Sensitive Networking (TSN) which enables high-bandwidth and low-latency communications in a mixed-criticality environment. In this work, we present Time-Sensitive Autonomous Architectures (TSAA) to enable TSN in ASDVs. The software architecture is based on a hypervisor providing strong isolation and virtual access to TSN for virtual machines (VMs). TSAA latest iteration includes an autonomous car controlled by two Xilinx accelerators and a multiport TSN switch. We discuss the engineering challenges and the performance evaluation of the project demonstrator. In addition, we propose a Proof-of-Concept design of virtualized TSN to enable multiple VMs executing on a single board taking advantage of the inherent guarantees offered by TSN

    Anpassen verteilter eingebetteter Anwendungen im laufenden Betrieb

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    The availability of third-party apps is among the key success factors for software ecosystems: The users benefit from more features and innovation speed, while third-party solution vendors can leverage the platform to create successful offerings. However, this requires a certain decoupling of engineering activities of the different parties not achieved for distributed control systems, yet. While late and dynamic integration of third-party components would be required, resulting control systems must provide high reliability regarding real-time requirements, which leads to integration complexity. Closing this gap would particularly contribute to the vision of software-defined manufacturing, where an ecosystem of modern IT-based control system components could lead to faster innovations due to their higher abstraction and availability of various frameworks. Therefore, this thesis addresses the research question: How we can use modern IT technologies and enable independent evolution and easy third-party integration of software components in distributed control systems, where deterministic end-to-end reactivity is required, and especially, how can we apply distributed changes to such systems consistently and reactively during operation? This thesis describes the challenges and related approaches in detail and points out that existing approaches do not fully address our research question. To tackle this gap, a formal specification of a runtime platform concept is presented in conjunction with a model-based engineering approach. The engineering approach decouples the engineering steps of component definition, integration, and deployment. The runtime platform supports this approach by isolating the components, while still offering predictable end-to-end real-time behavior. Independent evolution of software components is supported through a concept for synchronous reconfiguration during full operation, i.e., dynamic orchestration of components. Time-critical state transfer is supported, too, and can lead to bounded quality degradation, at most. The reconfiguration planning is supported by analysis concepts, including simulation of a formally specified system and reconfiguration, and analyzing potential quality degradation with the evolving dataflow graph (EDFG) method. A platform-specific realization of the concepts, the real-time container architecture, is described as a reference implementation. The model and the prototype are evaluated regarding their feasibility and applicability of the concepts by two case studies. The first case study is a minimalistic distributed control system used in different setups with different component variants and reconfiguration plans to compare the model and the prototype and to gather runtime statistics. The second case study is a smart factory showcase system with more challenging application components and interface technologies. The conclusion is that the concepts are feasible and applicable, even though the concepts and the prototype still need to be worked on in future -- for example, to reach shorter cycle times.Eine große Auswahl von Drittanbieter-Lösungen ist einer der Schlüsselfaktoren für Software Ecosystems: Nutzer profitieren vom breiten Angebot und schnellen Innovationen, während Drittanbieter über die Plattform erfolgreiche Lösungen anbieten können. Das jedoch setzt eine gewisse Entkopplung von Entwicklungsschritten der Beteiligten voraus, welche für verteilte Steuerungssysteme noch nicht erreicht wurde. Während Drittanbieter-Komponenten möglichst spät -- sogar Laufzeit -- integriert werden müssten, müssen Steuerungssysteme jedoch eine hohe Zuverlässigkeit gegenüber Echtzeitanforderungen aufweisen, was zu Integrationskomplexität führt. Dies zu lösen würde insbesondere zur Vision von Software-definierter Produktion beitragen, da ein Ecosystem für moderne IT-basierte Steuerungskomponenten wegen deren höherem Abstraktionsgrad und der Vielzahl verfügbarer Frameworks zu schnellerer Innovation führen würde. Daher behandelt diese Dissertation folgende Forschungsfrage: Wie können wir moderne IT-Technologien verwenden und unabhängige Entwicklung und einfache Integration von Software-Komponenten in verteilten Steuerungssystemen ermöglichen, wo Ende-zu-Ende-Echtzeitverhalten gefordert ist, und wie können wir insbesondere verteilte Änderungen an solchen Systemen konsistent und im Vollbetrieb vornehmen? Diese Dissertation beschreibt Herausforderungen und verwandte Ansätze im Detail und zeigt auf, dass existierende Ansätze diese Frage nicht vollständig behandeln. Um diese Lücke zu schließen, beschreiben wir eine formale Spezifikation einer Laufzeit-Plattform und einen zugehörigen Modell-basierten Engineering-Ansatz. Dieser Ansatz entkoppelt die Design-Schritte der Entwicklung, Integration und des Deployments von Komponenten. Die Laufzeit-Plattform unterstützt den Ansatz durch Isolation von Komponenten und zugleich Zeit-deterministischem Ende-zu-Ende-Verhalten. Unabhängige Entwicklung und Integration werden durch Konzepte für synchrone Rekonfiguration im Vollbetrieb unterstützt, also durch dynamische Orchestrierung. Dies beinhaltet auch Zeit-kritische Zustands-Transfers mit höchstens begrenzter Qualitätsminderung, wenn überhaupt. Rekonfigurationsplanung wird durch Analysekonzepte unterstützt, einschließlich der Simulation formal spezifizierter Systeme und Rekonfigurationen und der Analyse der etwaigen Qualitätsminderung mit dem Evolving Dataflow Graph (EDFG). Die Real-Time Container Architecture wird als Referenzimplementierung und Evaluationsplattform beschrieben. Zwei Fallstudien untersuchen Machbarkeit und Nützlichkeit der Konzepte. Die erste verwendet verschiedene Varianten und Rekonfigurationen eines minimalistischen verteilten Steuerungssystems, um Modell und Prototyp zu vergleichen sowie Laufzeitstatistiken zu erheben. Die zweite Fallstudie ist ein Smart-Factory-Demonstrator, welcher herausforderndere Applikationskomponenten und Schnittstellentechnologien verwendet. Die Konzepte sind den Studien nach machbar und nützlich, auch wenn sowohl die Konzepte als auch der Prototyp noch weitere Arbeit benötigen -- zum Beispiel, um kürzere Zyklen zu erreichen

    RegDspLib: Development of a C++ DSP common control library for Cancun, HL-LHC18kA and RF3kA power converters at CERN

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    English: The European Organization for Nuclear Research (CERN, Conseil Européen pour la Recherche Nucléaire in French), located in Geneva, Switzerland, hosts the largest particle accelerator complex in the world, which aims to push the boundaries of human knowledge on particle physics. The main acceleration technologies at CERN rely on radio-frequency (RF) cavities and superconducting electromagnets. Usually, these systems need to be fed from the grid using high-efficiency and high-precision switch-mode power electronic converters. This Master’s Thesis has been conducted to complete the Master's studies in Advanced Electronic Systems at the Univesity of the Basque Country (EHU/UPV, Universidad del País Vasco in Spanish). It has been carried out during a short-term internship at CERN’s System Department-Electric Power Converters-Low Power Converters (SY-EPC-LPC) group. This group is in charge of designing and developing low-voltage and high-current modular and compact converters, ranging from some Watts up to several kW. The SY-EPC-LPC manages a variety of power converters within the particle accelerator complex. Most digitally controlled ones share the same control hardware architecture consisting of a proprietary crate, named RegFGC3, which includes several cards. Among these, a Digital Signal Processor (DSP) regulation board and a State Control card containing a Field Programmable Gate Array (FPGA) can be highlighted. This RegFGC3 crate is part of a larger control platform, named FGC3. Although the hardware is highly standardized, nowadays each power supply uses converter-specific software for control purposes, coded in C programming language. This makes all code redundant, difficult to test, debug and maintain. Considering the aforementioned drawbacks, this Master's Thesis aims to design, develop and test a common control library which supports the regulation software of several power converters, providing standardization, flexibility and time-saving. To do so, as a first step, three of the accelerators' power converters have been selected: CANCUN (Cern Acdc Narrow CoNverter), HL-LHC18kA (High Luminosity Large Hadron Collider 18 kA) and RF3kA (Radio-Frequency 3 kA). This selection is based on that these converters incorporate a variety of operating and control requirements, i.e., 1-quadrant, 2-quadrant and 4-quadrant architectures, module parallelization, various current and voltage regulation loops, and different Pulse Width Modulation (PWM) modes including, in some cases, interleaving. After analysing the three power converters and their control (hardware and software), synergies have been identified, which are still missing at the software level. To provide a unified control software library that takes into account such synergies, the refactorization of the code from C to C++ has been justified as the best option. This approach allows using a fast and efficient Object Oriented Programming (OOP) language, whose nature facilitates the expression of the existing relationship between converter-specific codes. The main idea behind the proposed and implemented library, named RegDspLib, is based on constructing a parent class that supports all the converters. It contains all the shared similarities between converters, which eases the development of additional and specialized code. This base class allows the inheritance of the configured common features with the possibility of using, modifying, or adding what is needed by each converter in their corresponding derived classes. C++ language mechanisms have been used to correlate different classes, modules, methods and attributes of the code, easing the development of the common library. This, would have been more laborious in the C language. A variety of modules have been configured to provide logic to the classes, in which a generic module for the configuration of a generic Finite State Machine (FSM) template, and a regulation module with configurable PWM inputs are included, among others. Besides this and to make this library design possible, multiple modifications have been proposed. These consist of the design of a standard FSM for all the converters, the modification of the FPGA which is controlling and monitoring the power converter’s status, the interrupt handling on the DSP, and the building of new generic functions that work with multiple converters. The latter includes the slew rate method that controls the increasing/decreasing rate of the control algorithm’s reference value and an automatic parameter calculation script for interleaving control mechanisms. Verification of the RegDspLib library has been carried out using the CANCUN power converter. First, the same regulation response has been proved when comparing the original and the proposed library-based codes. Regarding digital resources, experimental results show an increase of only 2.48 % in the execution time of the program for the worst-case scenario, and up to a 24.63 % time-saving for the best-case. This demonstrates that it has been possible to standardize, refactor the code to C++ and add more features to the software without generating overruns. All things considered, the C++ programming language is proven valid for real-time control in the DSP target of CERN’s power converters. Besides, building a control library that groups all the common features has also provided a better-structured program, making it easier to understand and to work with. This work could lead to further improvements in the library and it can be completed in order to generalize it to control other power converters besides the presented ones. Moreover, although the RegDspLib library was originally aimed at the FGC3 control platform, this work provides the first steps for developing libraries taking into mind the future control hardware upgrade FGC4 (already in development). In such novel architecture, dedicated cards in the FGC3 (control, monitoring, regulation, measurement, etc.) will be replaced by one single main Central Processing Unit (CPU).Euskeraz: Ikerketa Nuklearrerako Europako Kontseilua (CERN, Conseil Européen pour la Recherche Nucléaire, frantsesez) Genevan (Suitza) dago kokatua. Partikula-fisikaren ezagutzaren mugak handitzea du helburu erakundeak. Horretarako, gaur egun munduko partikula azeleratzaile handiena dago bertan. CERNen erabiltzen diren azelerazio-teknologia nagusiak irrati-maiztasun (RF) kabitateak eta elektroiman supereroaleetan oinarritzen dira. Normalean, sistema horiek saretik hornitzen direnez, potentzia-bihurgailuak erabili behar dira. Oro har, bihurgailu horiek kommutatuak dira, eta eraginkortasun eta zehaztasun handiarekin operatzen dute. Euskal Herriko Unibertsitatearen (EHU/UPV) Sistema Elektroniko Aurreratuen masterra osatzeko helburuarekin burutu da master amaierako lan hau. CERNek unibertsitate-ikasleentzat duen praktika-programa baten testuinguruan garatu da lana, hain zuzen ere, Sistema Departamendua-Potentzia Bihurgailu Elektrikoak- Potentzia Baxuko Bihurgailu (SY-EPC-LPC) taldean. Bere izenak adierazten duen bezala, tentsio baxuko eta korronte altuko bihurgailu modularrak eta konpaktuak diseinatzeko eta garatzeko ardura du talde horrek. Bereziki, partikula-azeleradore konplexuaren parte diren bihurgailu ugari kudeatzen ditu SY-EPC-LPCek, Watt batzuetatik hasi eta zenbait kW-etaraino iristen direnak. Horien artean, hardware arkitektura berdina partekatzen dute digitalki kontrolaturiko bihurgailu gehienek, CERNen diseinatutako RegFGC3 modulua erabiltzen dutenak. Zenbait txartel elektronikok osatzen dute RegFGC3 modulua. Horien artean Seinale Digitalen Prozesadorea (DSP, Digital Signal Processor, ingelesez) duen erregulazio-txartela eta Ate-Matrize Programagarria (FPGA, Field Programmable Gate Array, ingelesez) daukan egoera-kontrol txartela nabarmentzen dira. Aldi berean, FGC3 izeneko bihurgailuen kontrolerako plataforma handiago baten parte da RegFGC3 moduloa. Hardwarea nahikoa estandarizatua dagoen arren, gaur egun bihurgailuetako bakoitzak bere kontrol-software espezifikoa erabiltzen du, C programazio-lengoaian idatzita. Horrek, erredundantzia eragiteaz gain, kodea frogatzeko, arazteko eta mantentzeko zailtasunak sortzen ditu. Aipatutako arazoak aztertu ondoren, master amaierako lanak bihurgailuen erregulazio-softwarea bateratzen duen kontrol-liburutegi amankomuna diseinatu, garatu eta frogatzea du helburu. Horrekin, estandarizazioa, malgutasuna eta denbora aurreztea bilatu da. Lehenengo urrats bezala, partikula-azeleradoreen parte diren hiru bihurgailu aukeratu dira: CANCUN (Cern Acdc Narrow CoNverter), HL-LHC18kA (High Luminosity Large Hadron Collider 18 kA) eta RF3kA (Radio-Frequency 3 kA). Bihurgailu ezberdinek duten aniztasuna hartzen da kontuan aukeraketa horretan. Hori da, 1, 2 eta 4-koadranteko arkitekturak aurki daitezke; horrez gain, korrontearen eta tentsioaren kontrolerako begizta eta Pultsu Zabalera bidezko Modulazio (PWM, Pulse Width Modulation ingelesez) algoritmo ezberdinak, zenbait kasutan, tartekatutako (interleaved, ingelesez) modulazio-eskemak barne. Behin hiru bihurgailuak eta horien kontrola aztertuta (hardware eta software mailan), sinergiak antzeman dira horien artean. Sinergiak kontuan hartzen dituen kontrol software-liburutegi amankomuna sortzeko, kodea C-tik C++-ra berreraikitzea justifikatu da aukerarik onena bezala. Horrek, Objektuetara Bideratutako Programazio-hizkuntza (OOP, Object Oriented Programming, ingelesez) azkar eta eraginkorra erabiltzea ahalbideratu du, programaren izaerak bihurgailuaren kode espezifikoen arteko erlazioen adierazpena sinplifikatuz. Proposatu eta inplementatutako RegDspLib izeneko liburutegian dagoen ideia nagusia da bihurgailu guztiei euskarria ematen dien funtsezko klase bat eraikitzean oinarritzen dela. Bihurgailuek partekatutako antzekotasun guztiak biltzen ditu klase horrek, eta kode gehigarria eta espezializatua garatzeko erraztasunak ematen ditu, konfiguratutako ezaugarri komunak heredatzea baimenduz. Liburutegi horrekin, bihurgailu bakoitzak behar duena erabiltzeko, aldatzeko edo gehitzeko aukera ematen da, klase deribatuen bidez. RegDspLib liburutegian C++ hizkuntzaren mekanismoak erabili dira klase, modulu, metodo eta atributu ezberdinak elkarrekin lotzeko. Garrantzitsua da aipatzea, nahiz eta helburu horiek lortzeko C programazio-hizkuntza erabiltzea posible izan, lana zailagoa izango litzatekeela. Elementu batzuk konfiguratzen dira klaseetan horiei logika emateko. Besteak beste, Egoera Finituko Makinak (FSM, Finite State Machine, ingelesez) konfiguratzeko modulu generiko bat eta PWM irteera konfiguragarriak dituen erregulazio-moduluak diseinatu dira. Horrez gain, aldaketa ugari burutu behar izan dira liburutegiaren diseinu egokia ahalbidetzeko. Horien artean hauexek nabarmen daitezke: FSM estandarra diseinatzea, potentzia-bihurgailuaren egoera kontrolatzen eta gainbegiratzen duen FPGAren programa-aldaketa, DSParen etenak kudeatzen eta, azkenik, bihurgailu anitzetan funtzionatzen duten funtzio generiko berriak sortzea. Funtzio berri horien artean kontrol algoritmoaren erreferentzia balioaren hazkunde/murrizketa abiadura kontrolatzen duen metodoa eta tartekatutako modulazio-mekanismoaren parametroak automatikoki kalkulatzen dituen funtzioa nabarmentzen dira, besteak beste. CANCUN potentzia-bihurgailuan gauzatu da RegDspLib liburutegiaren egiaztapena. Lehenik eta behin, korrontearen erreferentziari sistemak egindako jarraipenak frogatu du erregulazio-emaitza berdinak lortzen direla, bai proposatutako liburutegiarekin eta baita jatorrizko softwarearekin ere. Baliabide digitalei dagokienez, % 2,48ko exekuzio-denboraren gehikuntza erakutsi dute emaitza esperimentalek, kasurik okerrean, eta % 24,63ko murrizketa, kasurik onenean. Horrek guztiak frogatzen du posible dela, denbora-mugak gainditu gabe, kodea estandarizatzea, C++ lengoaiara berreraikiz, softwareari ezaugarriak gehituz. Laburbilduz, C++ programazio-lengoaia CERNen potentzia-bihurgailuak denbora errealean kontrolatzeko baliozkoa dela frogatu da. Gainera, ezaugarri amankomun guztiak biltzen dituen kontrol-liburutegi bat eraikitzeak, hobeto egituratutako programa bat sortu du, eta kodea hobeto ulertu eta honekin lan egitea erraztu du. Lan honetatik abiatuta, inplementatutako liburutegiaren hobekuntza gehigarriak garatu daitezke etorkizunean. Gainera, liburutegia beste bihurgailu batzuetan (aurkeztutakoez gain) erabiltzeko osatu daiteke. Azkenik, garrantzitsua da aipatzea, RegDspLib liburutegia FGC3 kontrol-plataformara bideratzeko asmoarekin sortu bada ere, proiektu honek FGC4 bertsiorako baliagarriak izango diren liburutegien garatze-ibilbidea hasi duela. Nabarmentzekoa da puntu hori, FGC3ko txartel espezifikoak (kontrola, ikuskapena, erregulazioa, neurketa, etab.) Prozesatzeko Unitate Zentral (CPU, Central Processing Unit, ingelesez) bakar batek ordezkatuko baititu FGC4n.Español: La Organización Europea para la Investigación Nuclear (CERN, Conseil Européen pour la Recherche Nucléaire, en francés) esta situada en Ginebra, Suiza. Tiene como objetivo superar los límites del conocimiento humano en física de partículas. Para poder cumplirlo, el CERN alberga actualmente el complejo de aceleradores de partículas más grande del mundo. Dentro de este, las principales tecnologías de aceleración se basan en cavidades de radiofrecuencia (RF) y electroimanes superconductores. En general, estos sistemas necesitan alimentarse de la red utilizando convertidores electrónicos de potencia, conmutados de alta eficiencia y precisión. Este Trabajo de Fin de Máster se ha llevado a cabo con el objetivo de completar los estudios del Máster en Sistemas Electrónicos Avanzados en la Universidad del País Vasco (EHU/UPV). Se ha realizado durante una estancia a través de un programa de prácticas del CERN, en el Departamento de Sistemas-Convertidores de Potencia Eléctricos-Baja Potencia (SY-EPC-LPC). Como su nombre indica, este grupo se encarga del diseño y desarrollo de convertidores modulares y compactos de baja tensión y alta corriente, que operan desde unos pocos Watt hasta varios kW. Este grupo gestiona una gran variedad de convertidores de potencia dentro del complejo de aceleradores de partículas. Entre estos, la mayoría de los controlados digitalmente comparten la misma arquitectura de hardware de control, que consiste en un módulo propietario, llamado RegFGC3. Este módulo incluye varias tarjetas, entre las que destacan una placa de regulación con un Procesador de Señal Digital (DSP, Digital Signal Processor, en inglés) y una tarjeta de control de estado que contiene una Matriz de Puertas Programable (FPGA, Field Programmable Gate Array, en inglés). A su vez, este módulo RegFGC3 forma parte de una plataforma de control mayor, llamada FGC3. Aunque el hardware esté estandarizado, actualmente cada uno de los convertidores utiliza un software de control específico, escrito en el lenguaje de programación C. Esto hace que el código resulte redundante y difícil de testear, depurar y mantener. Teniendo en cuenta las desventajas mencionadas, el objetivo del Trabajo de Fin de Máster ha sido diseñar, desarrollar y probar una librería de control común que englobe el software de regulación de varios convertidores de potencia, proporcionando estandarización, flexibilidad y ahorro de tiempo en el desarrollo de este. Para ello, como primer paso, se han seleccionado tres de los convertidores de potencia que forman parte de los aceleradores, CANCUN (Cern Acdc Narrow CoNverter), HL-LHC18kA (High Luminosity Large Hadron Collider 18 kA) y RF3kA (Radio-Frequency 3 kA). Esta selección se basa en que los convertidores incorporan arquitecturas de 1-cuadrante, 2-cuadrantes y 4-cuadrantes, distintos lazos de regulación de corriente y tensión, y varios modos de Modulación por Anchura de Pulso (PWM, Pulse Width Modulation, en inglés), incluyendo, en algunos casos, técnicas de entrelazamiento. Después de analizar los tres convertidores de potencia y su control (a nivel de hardware y software), se ha identificado una sinergia entre ellos, la cual falta a nivel de software. Para proporcionar una librería de software de control unificada que tenga en cuenta estas sinergias, se justifica la reescritura del código de C a C++ como la mejor opción. Esto permite utilizar un lenguaje de Programación Orientada a Objetos (OOP, Object Oriented Programming, en inglés) rápido y eficiente, cuya naturaleza facilita la expresión de la relación existente entre los códigos específicos del convertidor. La idea principal de la librería propuesta e implementada, llamada RegDspLib, se basa en la construcción de una clase padre que de soporte a todos los convertidores. Esta clase contiene todas las similitudes compartidas entre los convertidores, lo que facilita el desarrollo de código adicional y especializado al permitir la herencia de las características comunes configuradas. La librería posibilita utilizar, modificar o agregar lo que sea necesario para cada convertidor, a través de clases derivadas. Se han utilizado mecanismos del lenguaje C++ para correlacionar distintas clases, módulos, métodos y atributos del código, facilitando el desarrollo de una librería común. Esto hubiera sido más laborioso mediante el lenguaje de programación C. Con el objetivo de dotar de lógica a estas clases, se configuran una variedad de módulos. Se incluyen, entre otros, un módulo genérico para la configuración de Máquinas de Estados Finitas (FSM, Finite State Machine, en inglés) y un módulo de regulación con entradas PWM configurables. Además de esto, para posibilitar el diseño de la librería se han tenido que realizar múltiples modificaciones. Estas incluyen el diseño de una FSM estándar, la modificación de la FPGA que controla y supervisa el estado del convertidor de potencia, el manejo de interrupciones en la DSP y la creación de nuevas funciones genéricas que sirvan para múltiples convertidores. Entre estas últimas destacan el método de tasa de variación que controla el ratio de aumento/disminución del valor de referencia del algoritmo de control y el cálculo automático de los parámetros del mecanismo de control de entrelazamiento. La verificación de la librería RegDspLib se ha llevado a cabo en el convertidor de potencia CANCUN. Por un lado, se ha obtenido la misma respuesta al escalón de entrada de corriente, tanto con la librería propuesta como con el software original. Por otro, los resultados experimentales muestran un aumento del 2,48 %, en el tiempo de ejecución, para el peor de los casos, y una reducción de hasta el 24,63 %, en el mejor. Esto demuestra que ha sido posible estandarizar, reescribir el código a C++ y agregar características adicionales al software sin exceder los límites de tiempo. En resumen, el lenguaje de programación C++ se ha demostrado como válido para el control en tiempo real de los convertidores de potencia del CERN a través de la regulación en la DSP. Además, la construcción de una librería de control que engloba todas las características comunes ha proporcionado un programa mejor estructurado, lo que facilita su comprensión y trabajar con el mismo. En un futuro, este proyecto podría llevar a mejoras adicionales de la librería y ser completado para su utilización con otros convertidores de potencia, además de con los tres presentados. Por último, aunque la librería RegDspLib estaba originalmente destinada a la plataforma de control FGC3, este proyecto marca los primeros pasos hacia el desarrollo de librerías para la futura actualización del FGC4, donde las tarjetas dedicadas del FGC3 (control, supervisión, regulación, medición, etc.) serán reemplazadas por una sola Unidad Central de Procesamiento (CPU, Central Processing Unit, en inglés) principal.Français: Le Conseil Européen Pour la Recherche Nucléaire (CERN), situé à Genève, Suisse, abrite le plus grand complexe d'accélérateurs de particules au monde, qui vise à repousser les limites de la connaissance humaine en matière de physique des particules. Les principales technologies d'accélération du CERN reposent sur des cavités radiofréquences (RF) et les électro-aimants supraconducteurs. Ces systèmes doivent être alimentés par le réseau à l'aide de convertisseurs électroniques de puissance à découpage, à haut rendement et haute précision. Ce mémoire de maîtrise a été réalisé afin de compléter les études de maîtrise en systèmes électroniques avancés à L'Université du Pays Basque (EHU/UPV, Universidad del Pais Vasco en espagnol). Le projet a été réalisé à la suite d’un stage de courte durée dans le groupe System Department-Electric Power Converters-Low Power Converters (SY-EPC-LPC). Au sein du CERN, comme son nom l'indique, SY-EPC-LPC est chargé de concevoir et de développer des convertisseurs modulaires et compacts à basse tension et à courant élevé, d'une puissance allant de quelques Watts à plusieurs kW. Ce groupe gère une variété de convertisseurs de puissance au sein du complexe d'accélérateurs de particules. Ces convertisseurs partagent la même architecture matérielle de contrôle, qui consiste en un boîtier propriétaire, appelé RegFGC3, comprenant plusieurs cartes, dont une carte de régulation à processeur de signal numérique (DSP, Digital Signal Processor en anglais) et une carte de contrôle d'état contenant une réseau de portes programmables sur site (FPGA, Field Programmable Gate Array en anglais). Ce boîtier RegFGC3 fait partie d'une plateforme de contrôle plus large appelée FGC3, qui contrôle le convertisseur de puissance. Bien que le matériel soit fortement standardisé, aujourd’hui, chacun convertisseur utilise un logiciel spécifique au convertisseur à des fins de contrôle, écrite à l'origine dans le langage de programmation C. Cela rend tout le code redondant et difficile à tester, à déboguer et à entretenir. En tenant compte des inconvénients

    SplITS: Split Input-to-State Mapping for Effective Firmware Fuzzing

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    Ability to test firmware on embedded devices is critical to discovering vulnerabilities prior to their adversarial exploitation. State-of-the-art automated testing methods rehost firmware in emulators and attempt to facilitate inputs from a diversity of methods (interrupt driven, status polling) and a plethora of devices (such as modems and GPS units). Despite recent progress to tackle peripheral input generation challenges in rehosting, a firmware's expectation of multi-byte magic values supplied from peripheral inputs for string operations still pose a significant roadblock. We solve the impediment posed by multi-byte magic strings in monolithic firmware. We propose feedback mechanisms for input-to-state mapping and retaining seeds for targeted replacement mutations with an efficient method to solve multi-byte comparisons. The feedback allows an efficient search over a combinatorial solution-space. We evaluate our prototype implementation, SplITS, with a diverse set of 21 real-world monolithic firmware binaries used in prior works, and 3 new binaries from popular open source projects. SplITS automatically solves 497% more multi-byte magic strings guarding further execution to uncover new code and bugs compared to state-of-the-art. In 11 of the 12 real-world firmware binaries with string comparisons, including those extensively analyzed by prior works, SplITS outperformed, statistically significantly. We observed up to 161% increase in blocks covered and discovered 6 new bugs that remained guarded by string comparisons. Significantly, deep and difficult to reproduce bugs guarded by comparisons, identified in prior work, were found consistently. To facilitate future research in the field, we release SplITS, the new firmware data sets, and bug analysis at https://github.com/SplITS-FuzzerComment: Accepted ESORICS 202
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