13,979 research outputs found
Secure Cascade Channel Synthesis
We consider the problem of generating correlated random variables in a
distributed fashion, where communication is constrained to a cascade network.
The first node in the cascade observes an i.i.d. sequence locally before
initiating communication along the cascade. All nodes share bits of common
randomness that are independent of . We consider secure synthesis - random
variables produced by the system appear to be appropriately correlated and
i.i.d. even to an eavesdropper who is cognizant of the communication
transmissions. We characterize the optimal tradeoff between the amount of
common randomness used and the required rates of communication. We find that
not only does common randomness help, its usage exceeds the communication rate
requirements. The most efficient scheme is based on a superposition codebook,
with the first node selecting messages for all downstream nodes. We also
provide a fleeting view of related problems, demonstrating how the optimal rate
region may shrink or expand.Comment: Submitted to IEEE Transactions on Information Theor
CMOS design of chaotic oscillators using state variables: a monolithic Chua's circuit
This paper presents design considerations for monolithic implementation of piecewise-linear (PWL) dynamic systems in CMOS technology. Starting from a review of available CMOS circuit primitives and their respective merits and drawbacks, the paper proposes a synthesis approach for PWL dynamic systems, based on state-variable methods, and identifies the associated analog operators. The GmC approach, combining quasi-linear VCCS's, PWL VCCS's, and capacitors is then explored regarding the implementation of these operators. CMOS basic building blocks for the realization of the quasi-linear VCCS's and PWL VCCS's are presented and applied to design a Chua's circuit IC. The influence of GmC parasitics on the performance of dynamic PWL systems is illustrated through this example. Measured chaotic attractors from a Chua's circuit prototype are given. The prototype has been fabricated in a 2.4- mu m double-poly n-well CMOS technology, and occupies 0.35 mm/sup 2/, with a power consumption of 1.6 mW for a +or-2.5-V symmetric supply. Measurements show bifurcation toward a double-scroll Chua's attractor by changing a bias current
Interfacing PDM sensors with PFM spiking systems: application for Neuromorphic Auditory Sensors
In this paper we present a sub-system to convert
audio information from low-power MEMS microphones with
pulse density modulation (PDM) output into rate coded spike
streams. These spikes represent the input signal of a Neuromorphic
Auditory Sensor (NAS), which is implemented with Spike
Signal Processing (SSP) building blocks. For this conversion, we
have designed a HDL component for FPGA able to interface
with PDM microphones and converts their pulses to temporal
distributed spikes following a pulse frequency modulation (PFM)
scheme with an accurate configurable Inter-Spike-Interval. The
new FPGA component has been tested in two scenarios, first as a
stand-alone circuit for its characterization, and then it has been
integrated with a full NAS design to verify its behavior. This
PDM interface demands less than 1% of a Spartan 6 FPGA
resources and has a power consumption below 5mW.Ministerio de Economía y Competitividad TEC2016-77785-
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