For a task mapped to the reconfigurable fabric (RF) of a partially reconfigurable hybrid processor architecture, significant speedup can be obtained if multiple processing units (PUs) are used to accelerate the task. In this paper, we present the results obtained from a quantitative analysis for a single data-parallel task mapped to the RF of a busbased hybrid processor architecture. The architectural constraints in this case include run-time reconfiguration delay and a shared data bus to main memory. 1