Effect of impact ionization in scaled pHEMTs

The effect of impact ionization on pseudomorphic high electron mobility transistors is studied using Monte Carlo simulations when these devices are scaled into deep decanano dimensions. The scaling of devices with gate lengths of 120, 90, 70, 50 and 30 nm has been performed in both lateral and vertical directions. The impact ionization is treated as an additional scattering mechanism in the Monte Carlo module. The critical drain voltage, at which device characteristics begin to indicate breakdown, decreases as the gate voltage is lowered. Similarly, the breakdown drain voltage is also found to decrease during the scaling process

Characterization and Digital Signal Integrity Analysis of PHEMTs using an Eye Diagram

Digital Performance analysis of high electron devices used in microwave communication systems is crucial for ensuring their suitability to ever-increasing high-speed data rate applications. This study aims at characterizing a 0.5x200μm dimension pseudomorphic heterojunction transistor and studying the effect of the device characteristics on various parameters of digital bit streams. It has been found that while the device can be predicted to be suitable for a wide range analog bandwidth application however digital application can be satisfactory only in a narrower range only and that a correlation has been established between digital bit rate and various small signal parameters of the device

The development of sub-25 nm III-V High Electron Mobility Transistors

High Electron Mobility Transistors (HEMTs) are crucially important devices in microwave circuit applications. As the technology has matured, new applications have arisen, particularly at millimetre-wave and sub-millimetre wave frequencies. There now exists great demand for low-visibility, security and medical imaging in addition to telecommunications applications operating at frequencies well above 100 GHz. These new applications have driven demand for high frequency, low noise device operation; key areas in which HEMTs excel. As a consequence, there is growing incentive to explore the ultimate performance available from such devices. As with all FETs, the key to HEMT performance optimisation is the reduction of gate length, whilst optimally scaling the rest of the device and minimising parasitic extrinsic influences on device performance. Although HEMTs have been under development for many years, key performance metrics have latterly slowed in their evolution, largely due to the difficulty of fabricating devices at increasingly nanometric gate lengths and maintaining satisfactory scaling and device performance. At Glasgow, the world-leading 50 nm HEMT process developed in 2003 had not since been improved in the intervening five years. This work describes the fabrication of sub-25 nm HEMTs in a robust and repeatable manner by the use of advanced processing techniques: in particular, electron beam lithography and reactive ion etching. This thesis describes firstly the development of robust gate lithography for sub-25 nm patterning, and its incorporation into a complete device process flow. Secondly, processes and techniques for the optimisation of the complete device are described. This work has led to the successful fabrication of functional 22 nm HEMTs and the development of 10 nm scale gate pattern transfer: simultaneously some of the shortest gate length devices reported and amongst the smallest scale structures ever lithographically defined on III-V substrates. The first successful fabrication of implant-isolated planar high-indium HEMTs is also reported amongst other novel secondary processes

Scaling of pHEMTs to Decanano Dimensions

The effect of scaling into deep decanano dimensions on the performance of pseudomorphic high electron mobility transistors (pHEMTs) is extensively studied using Monte Carlo simulations. The scaling of devices with gate lengths of 120, 70, 50 and 30nm is performed in both lateral and vertical directions. The devices exhibit a significant improvement in transconductance during scaling, even though external resistances become a limiting factor

Scaling of pHEMTs to Decanano Dimensions

The effect of scaling into deep decanano dimensions on the performance of pseudomorphic high electron mobility transistors (pHEMTs) is extensively studied using Monte Carlo simulations. The scaling of devices with gate lengths of 120, 70, 50 and 30nm is performed in both lateral and vertical directions. The devices exhibit a significant improvement in transconductance during scaling, even though external resistances become a limiting factor