Accelerated Aging in Devices and Circuits

abstract: The aging mechanism in devices is prone to uncertainties due to dynamic stress conditions. In AMS circuits these can lead to momentary fluctuations in circuit voltage that may be missed by a compact model and hence cause unpredictable failure. Firstly, multiple aging effects in the devices may have underlying correlations. The generation of new traps during TDDB may significantly accelerate BTI, since these traps are close to the dielectric-Si interface in scaled technology. Secondly, the prevalent reliability analysis lacks a direct validation of the lifetime of devices and circuits. The aging mechanism of BTI causes gradual degradation of the device leading to threshold voltage shift and increasing the failure rate. In the 28nm HKMG technology, contribution of BTI to NMOS degradation has become significant at high temperature as compared to Channel Hot Carrier (CHC). This requires revising the End of Lifetime (EOL) calculation based on contribution from induvial aging effects especially in feedback loops. Conventionally, aging in devices is extrapolated from a short-term measurement, but this practice results in unreliable prediction of EOL caused by variability in initial parameters and stress conditions. To mitigate the extrapolation issues and improve predictability, this work aims at providing a new approach to test the device to EOL in a fast and controllable manner. The contributions of this thesis include: (1) based on stochastic trapping/de-trapping mechanism, new compact BTI models are developed and verified with 14nm FinFET and 28nm HKMG data. Moreover, these models are implemented into circuit simulation, illustrating a significant increase in failure rate due to accelerated BTI, (2) developing a model to predict accelerated aging under special conditions like feedback loops and stacked inverters, (3) introducing a feedback loop based test methodology called Adaptive Accelerated Aging (AAA) that can generate accurate aging data till EOL, (4) presenting simulation and experimental data for the models and providing test setup for multiple stress conditions, including those for achieving EOL in 1 hour device as well as ring oscillator (RO) circuit for validation of the proposed methodology, and (5) scaling these models for finding a guard band for VLSI design circuits that can provide realistic aging impact.Dissertation/ThesisMasters Thesis Electrical Engineering 201

Ultra-small low power temperature-to-digital converter and verification methods of analog circuit with Trojan states

Accurate, small and low-power CMOS temperature sensors designed for multi-position temperature monitoring of power management in multi-core processors are proposed. The temperature sensors utilize the temperature characteristics of the threshold voltage of a MOS transistors to sense temperature and are highly linear from 60°C to 90°C. This is the temperature range needed for the power management applications where temperature sensors are strategically placed at multiple locations in each core to protect the processor from temperature-induced reliability degradation. A temperature-to-digital converter (TDC) that does not require either a reference generator or an ADC is also introduced, and it exhibits low supply sensitivity, small die area, and low power consumption. Both analog threshold voltage based temperature sensor and a prototype TDC designed to support multi-position thermal-sensing for power management applications from 60°C to 90°C are implemented in an IBM 0.13μm CMOS process with a 1.2V power supply. A new verification approach with several variants for identifying the number of stable equilibrium points in supply-insensitive bias generators, references, and temperature sensors based upon self-stabilized feedback loops is introduced. This provides a simple and practical method for determining if these circuits require a “start-up” circuit and, if needed, for verifying that the startup circuit is effective at eliminating undesired stable equilibrium points in the presence of process and temperature variations. These undesired stable equilibrium points are often referred to as Trojan states. It will be shown that some widely used approaches for verification do not guarantee Trojan states have been removed. Some of the methods introduced appear to be more practical to work with than others. A group of benchmark circuit with Trojan states will be introduced and used to demonstrate the effectiveness of the new method