Heuristics Based Test Overhead Reduction Techniques in VLSI Circuits

The electronic industry has evolved at a mindboggling pace over the last five decades. Moore’s Law [1] has enabled the chip makers to push the limits of the physics to shrink the feature sizes on Silicon (Si) wafers over the years. A constant push for power-performance-area (PPA) optimization has driven the higher transistor density trends. The defect density in advanced process nodes has posed a challenge in achieving sustainable yield. Maintaining a low Defect-per-Million (DPM) target for a product to be viable with stringent Time-to-Market (TTM) has become one of the most important aspects of the chip manufacturing process. Design-for-Test (DFT) plays an instrumental role in enabling low DPM. DFT however impacts the PPA of a chip. This research describes an approach of minimizing the scan test overhead in a chip based on circuit topology heuristics. These heuristics are applied on a full-scan design to convert a subset of the scan flip-flops (SFF) into D flip-flops (DFF). The K Longest Path per Gate (KLPG) [2] automatic test pattern generation (ATPG) algorithm is used to generate tests for robust paths in the circuit. Observability driven multi cycle path generation [3][4] and test are used in this work to minimize coverage loss caused by the SFF conversion process. The presence of memory arrays in a design exacerbates the coverage loss due to the shadow cast by the array on its neighboring logic. A specialized behavioral modeling for the memory array is required to enable test coverage of the shadow logic. This work develops a memory model integrated into the ATPG engine for this purpose. Multiple clock domains pose challenges in the path generation process. The inter-domain clocking relationship and corresponding logic sensitization are modeled in our work to generate synchronous inter-domain paths over multiple clock cycles. Results are demonstrated on ISCAS89 and ITC99 benchmark circuits. Power saving benefit is quantified using an open-source standard-cell library

Tecniche di Test Innovative per la Caratterizzazione di Memorie a Gate Flottante

L\u2019affidabilit\ue0 nella ritenzione dei dati memorizzati \ue8 una delle problematiche fondamentali delle memorie flash; esse vengono normalmente testate, in produzione con procedure specifiche implementate su ATE (Automated Test Equipments), per rilevare problemi di lettura, programmazione e cancellazione; vengono inoltre provate altre procedure per identificare possibili faults e per il corretto trimming dei parametri interni. Oggi, il testing classico con ATE \ue8 supportato dalle tecniche BIST (Built-In-Self-Test), tramite le quali si prevede in progetto, all\u2019interno dei circuiti integrati, una parte di hardware e software supplementari per permettere l\u2019auto-test (funzionale e/o parametrico), cos\uec da ridurre la dipendenza da apparecchiature ATE esterne e quindi riducendo sensibilmente il tempo di esecuzione del test completo e permettendo la realizzazione di test del circuito integrato in qualsiasi istante e condizione di funzionamento (in-field test). Un ulteriore passo avanti nel testing in-field \ue8 stato effettuato con lo sviluppo delle tecniche SBST (Software-Based Self Test), che si basano sull\u2019uso del microprocessore interno alla memoria per effettuare i test necessari via software, senza avere cos\uec la necessit\ue0 di progettare e realizzare nel chip hardware aggiuntivo, cos\uec come accade nel caso di presenza di strutture BIST all\u2019interno del circuito. Rispetto allo stato dell\u2019arte delle tecniche di testing si \ue8 approfondito lo studio, la progettazione e la realizzazione di una soluzione circuitale innovativa denominata Portable-ATE per il testing dei Memory Test Chip. La scheda Portable-ATE \ue8 stata sviluppata partendo da una demo-board STM32-Nucleo (STM32F072RB) ed aggiungendo una scheda custom che permette di gestire il sistema di alimentazione, la corretta comunicazione con il memory test chip e l\u2019alloggiamento del test chip stesso. Essa \ue8 in grado di valutare le perfomances di un singolo memory test-chip mantenendo gli stessi standard di affidabilit\ue0 e riproducibilit\ue0 di un ATE classico, aggiungendo portabilit\ue0, flessibilit\ue0, configurabilit\ue0 e la possibilit\ue0 di sviluppo e debug di algoritmi di gestione e software-based self test (SBST) con logging in tempo reale. Con l\u2019utilizzo del Portable-ATE \ue8 stata effettuata la caratterizzazione di alcuni memory test chip di STMicroelectronics con particolare attenzione alle analisi di stress, quale gate e drain stress e successivamente sono stati effettuati test di ciclatura per verificare la ritenzione dei dati; per valutare i test effettuati sono state estratte le distribuzioni di soglia. Infine, grazie all\u2019utilizzo del Portable ATE \ue8 stato possibile sviluppare, testare e ottimizzare gli algoritmi di gestione della memoria, program con verify, erase con verify e refresh senza avere all\u2019interno della memoria nessun PEC (Program/Erase Controller) o microprocessore interno per la gestione degli stessi e con la possibilit\ue0, totalmente innovativa, di avere un logging in tempo reale delle operazioni in esecuzione

SW-Based Transparent In-Field Memory Testing

With continuous technology scaling, both quality and reliability are becoming major concerns for ICs due to extreme variations, non-ideal voltage scaling, etc. (not to mention the business pressure leading to shorter-time to market). One-time-factory manufacturing test is not sufficient anymore, and in-field testing (e.g., periodically, at power-on, during idle times) is becoming mandatory. Due to the strict constraints of in-field test, transparent BIST is extremely attractive, since it allows to minimize test invasiveness. This paper presents a cheap, high quality and practical SW-based transparent in-field test approach for memories within a system. Instead of using hardware BIST, the proposed scheme re-uses the CPU to perform in-field testing for all memories within the system. All quality metrics of the proposed solution (such as defect coverage, test time and code size) are analyzed. Case studies using the ARM instruction set architecture are provided to demonstrate the applicability of the solution. With the proposed approach no hardware BIST is necessary and speed-related faults are tackled, whereas results show the test time complexity of the SW-based transparent tests is the same as the one of the standard hardware BIST test. Moreover, data previously present in the memory is not corrupted with, in average, only a 30% increase in test program size with respect to non-transparent SW-based test

SW-Based Transparent In-Field Memory Testing

With continuous technology scaling, both quality and reliability are becoming major concerns for ICs due to extreme variations, non-ideal voltage scaling, etc. (not to mention the business pressure leading to shorter-time to market). One-time-factory manufacturing test is not sufficient anymore, and in-field testing (e.g., periodically, at power-on, during idle times) is becoming mandatory. Due to the strict constraints of in-field test, transparent BIST is extremely attractive, since it allows to minimize test invasiveness. This paper presents a cheap, high quality and practical SW-based transparent in-field test approach for memories within a system. Instead of using hardware BIST, the proposed scheme re-uses the CPU to perform in-field testing for all memories within the system. All quality metrics of the proposed solution (such as defect coverage, test time and code size) are analyzed. Case studies using the ARM instruction set architecture are provided to demonstrate the applicability of the solution. With the proposed approach no hardware BIST is necessary and speed-related faults are tackled, whereas results show the test time complexity of the SW-based transparent tests is the same as the one of the standard hardware BIST test. Moreover, data previously present in the memory is not corrupted with, in average, only a 30% increase in test program size with respect to non-transparent SW-based test