SRAM Local Bit Line Access Failure Analyses

Abstract — Due to the increasing process parameter variations different peripheral circuit style is necessary in the design and bitline capacitance, design of fast, reliable and robust read/write circuits for nanoscale SRAMs is a challenge. In this paper, we have investigated the effect of threshold voltage variations on the stability of read and write access schemes in SRAM designs. We considered three small signal read out and phase to ensure a good yield. In this paper, we analyze the different dynamic failure mechanisms oF SRAM designs in an advanced technology to understand the impact of process parameter variations on two write schemes to establish the SRAM local bitline failure the stability of memory cells. The findings from these failure trends and behavior under aggressive timing constraints and in the presence of process variations. The critical transistors in both the memory cell and the sense circuits are determined using corner analyses. Detailed simulation analyses are then performed by randomly varying the threshold voltages of these analyses can be used in the early design cycle to optimize the design for yield enhancement. We consider three sense amplifier designs and two different write architectures in our analyses. We finally present detailed simulation results for the critical transistors, and the failing probabilities and points are above designs and discuss the impact of the different design then determined. Observations and conclusions on the failure trends of both the read and write operations are presented. styles and architectures on the cell failure probability and memory yield. The SRAM cell used in our analyses has a I