36,511 research outputs found
Yield-improving test and routing circuits for a novel 3-D interconnect technology
This work presents a system to increase the yield of a novel 3-D chip integration technology. A built-in self-test and a routing system have been developed to identify and avoid faults on vertical connections between different stacked chips. The 3-D technology is based on stacking several active CMOS-ICs, which have through-substrate electrical contacts to communicate with each other. The expected defects of these vias are shorts and resistances that are too high. <P> The test and routing system is designed to analyze an arbitrary number of connections. The result ist used to gain information about the reliability of the new 3-D processing and to increase its yield. The circuits have been developed in 0.13 μm technology, one chip has been fabricated and tested, another one is in production
A scalable multi-core architecture with heterogeneous memory structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs)
Neuromorphic computing systems comprise networks of neurons that use
asynchronous events for both computation and communication. This type of
representation offers several advantages in terms of bandwidth and power
consumption in neuromorphic electronic systems. However, managing the traffic
of asynchronous events in large scale systems is a daunting task, both in terms
of circuit complexity and memory requirements. Here we present a novel routing
methodology that employs both hierarchical and mesh routing strategies and
combines heterogeneous memory structures for minimizing both memory
requirements and latency, while maximizing programming flexibility to support a
wide range of event-based neural network architectures, through parameter
configuration. We validated the proposed scheme in a prototype multi-core
neuromorphic processor chip that employs hybrid analog/digital circuits for
emulating synapse and neuron dynamics together with asynchronous digital
circuits for managing the address-event traffic. We present a theoretical
analysis of the proposed connectivity scheme, describe the methods and circuits
used to implement such scheme, and characterize the prototype chip. Finally, we
demonstrate the use of the neuromorphic processor with a convolutional neural
network for the real-time classification of visual symbols being flashed to a
dynamic vision sensor (DVS) at high speed.Comment: 17 pages, 14 figure
A Power-Efficient 3-D On-Chip Interconnect for Multi-Core Accelerators with Stacked L2 Cache
The use of multi-core clusters is a promising option for data-intensive embedded applications such as multi-modal sensor fusion, image understanding, mobile augmented reality. In this paper, we propose a power-efficient 3-D on-chip interconnect for multi-core clusters with stacked L2 cache memory. A new switch design makes a circuit-switched Mesh-of-Tree (MoT) interconnect reconfigurable to support power-gating of processing cores, memory blocks, and unnecessary interconnect resources (routing switch, arbitration switch, inverters placed along the on-chip wires). The proposed 3-D MoT improves the power efficiency up to 77% in terms of energy-delay product (EDP)
Discrete analogue computing with rotor-routers
Rotor-routing is a procedure for routing tokens through a network that can
implement certain kinds of computation. These computations are inherently
asynchronous (the order in which tokens are routed makes no difference) and
distributed (information is spread throughout the system). It is also possible
to efficiently check that a computation has been carried out correctly in less
time than the computation itself required, provided one has a certificate that
can itself be computed by the rotor-router network. Rotor-router networks can
be viewed as both discrete analogues of continuous linear systems and
deterministic analogues of stochastic processes.Comment: To appear in Chaos Special Focus Issue on Intrinsic and Designed
Computatio
Quarc: a novel network-on-chip architecture
This paper introduces the Quarc NoC, a novel NoC architecture inspired by the Spidergon NoC. The Quarc scheme significantly outperforms the Spidergon NoC through balancing the traffic which is the result of the modifications applied to the topology and the routing elements.The proposed architecture is highly efficient in performing collective communication operations including broadcast and multicast. We present the topology, routing discipline and switch architecture for the Quarc NoC and demonstrate the performance with the results obtained from discrete event simulations
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