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1 research outputs found
Round-trip latency prediction for memory access fairness in mesh-based many-core architectures
Author
Hengzhu Liu
Xiaohui Zhao
+3Â more
Xiaowen Chen
Yang Li
Yong Yang
Publication venue
'Institute of Electronics, Information and Communications Engineers (IEICE)'
Publication date
01/01/2014
Field of study
No full text
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