A logic-based approach for the verification of UML timed models

This article presents a novel technique to formally verify models of real-time systems captured through a set of heterogeneous UML diagrams. The technique is based on the following key elements: (i) a subset of Unified Modeling Language (UML) diagrams, called Coretto UML (C-UML), which allows designers to describe the components of the system and their behavior through several kinds of diagrams (e.g., state machine diagrams, sequence diagrams, activity diagrams, interaction overview diagrams), and stereotypes taken from the UML Profile for Modeling and Analysis of Real-Time and Embedded Systems; (ii) a formal semantics of C-UML diagrams, defined through formulae of the metric temporal logic Tempo Reale ImplicitO (TRIO); and (iii) a tool, called Corretto, which implements the aforementioned semantics and allows users to carry out formal verification tasks on modeled systems. We validate the feasibility of our approach through a set of different case studies, taken from both the academic and the industrial domain

Roles at the Basis of UML Validation

Formal validation of UML models proves to be hardly realizable, due to the imprecise semantics of UML dynamic diagrams. To remedy that, we first present a technique for transforming UML statecharts into Petri nets. We develop afterwards, an approach based on the movement of the objects throughout the roles they play. This approach allows validation of the temporal logic properties translated from the OCL invariants, on the Petri nets derived from the UML models. System property validation is realized thanks to a prior initialization of the objects and exchanged messages between the communicating objects. A case study is given to illustrate the methodology