Robust VLSI Architecture for System-On-Chip Design and its implementation in Viterbi Decoder

Abstract — This paper presents robust VLSI architecture which avoids most of malfunctions and makes the system work correctly. The proposed architecture realizes robustness only by using small switches. The switches avoid the broken computing modules and reconfigure data flows between the other normal modules. This architecture has the advantages compared to conventional duplicated systems in terms of resource utilization and circuit area, and improves yield rate. We designed the Viterbi decoder based on the proposed robust architecture and evaluated its effectiveness in CMOS technology. I