2,126 research outputs found
Synthesis of Quantum Logic Circuits
We discuss efficient quantum logic circuits which perform two tasks: (i)
implementing generic quantum computations and (ii) initializing quantum
registers. In contrast to conventional computing, the latter task is nontrivial
because the state-space of an n-qubit register is not finite and contains
exponential superpositions of classical bit strings. Our proposed circuits are
asymptotically optimal for respective tasks and improve published results by at
least a factor of two.
The circuits for generic quantum computation constructed by our algorithms
are the most efficient known today in terms of the number of expensive gates
(quantum controlled-NOTs). They are based on an analogue of the Shannon
decomposition of Boolean functions and a new circuit block, quantum
multiplexor, that generalizes several known constructions. A theoretical lower
bound implies that our circuits cannot be improved by more than a factor of
two. We additionally show how to accommodate the severe architectural
limitation of using only nearest-neighbor gates that is representative of
current implementation technologies. This increases the number of gates by
almost an order of magnitude, but preserves the asymptotic optimality of gate
counts.Comment: 18 pages; v5 fixes minor bugs; v4 is a complete rewrite of v3, with
6x more content, a theory of quantum multiplexors and Quantum Shannon
Decomposition. A key result on generic circuit synthesis has been improved to
~23/48*4^n CNOTs for n qubit
Techniques for the Synthesis of Reversible Toffoli Networks
This paper presents novel techniques for the synthesis of reversible networks
of Toffoli gates, as well as improvements to previous methods. Gate count and
technology oriented cost metrics are used. Our synthesis techniques are
independent of the cost metrics. Two new iterative synthesis procedure
employing Reed-Muller spectra are introduced and shown to complement earlier
synthesis approaches. The template simplification suggested in earlier work is
enhanced through introduction of a faster and more efficient template
application algorithm, updated (shorter) classification of the templates, and
presentation of the new templates of sizes 7 and 9. A novel ``resynthesis''
approach is introduced wherein a sequence of gates is chosen from a network,
and the reversible specification it realizes is resynthesized as an independent
problem in hopes of reducing the network cost. Empirical results are presented
to show that the methods are effective both in terms of the realization of all
3x3 reversible functions and larger reversible benchmark specifications.Comment: 20 pages, 5 figure
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