Explorations for Efficient Reversible Barrel Shifters and Their Mappings in QCA Nanocomputing

This thesis is based on promising computing paradigm of reversible logic which generates unique outputs out of the inputs and. Reversible logic circuits maintain one-to-one mapping inside of the inputs and the outputs. Compared to the traditional irreversible computation, reversible logic circuit has the advantage that it successfully avoids the information loss during computations. Also, reversible logic is useful to design ultra-low-power nanocomputing circuits, circuits for quantum computing, and the nanocircuits that are testable in nature. Reversible computing circuits require the ancilla inputs and the garbage outputs. Ancilla input is the constant input in reversible circuits. Garbage output is the output for maintaining the reversibility of the reversible logic but is not any of the primary inputs nor a useful bit. An efficient reversible circuit will have the minimal number of garbage and ancilla bits. Barrel shifter is one of main computing systems having applications in high speed digital signal processing, oating-point arithmetic, FPGA, and Center Processing Unit (CPU). It can operate the function of shifting or rotation for multiple bits in only one clock cycle. The goal of this thesis is to design barrel shifters based on the reversible computing that are optimized in terms of the number of ancilla and garbage bits. In order to achieve this goal, a new Super Conservative Reversible Logic Gate (SCRL gate) has been used. The SCRL gate has 1 control input depending on the value of which it can swap any two n-1 data inputs. We proved that the SCRL gate is superior to the existing conservative reversible Fredkin gate. This thesis develops 5 design methodologies for reversible barrel shifters using SCRL gates that are primarily optimized with the criteria of the number of ancilla and garbage bits. The five proposed methodologies consist of reversible right rotator, reversible logical right shifter, reversible arithmetic right shifter, reversible universal right shifter and reversible universal bidirectional shifter. The proposed reversible barrel shifter design is compared with the existing works in literature and have shown improvement ranging from 8.5% to 92% by the number of garbage and ancilla bits. The SCRL gate and design methodologies of reversible barrel shifter are mapped in Quantum Dot Cellular Automata (QCA) computing. It is illustrated that the SCRL-based designs of reversible barrel shifters have less QCA cost (cost in terms of number of inverters and majority voters) compared to the Fredkin gate- based designs of reversible barrel shifters

Heat Dissipation Bounds for Nanocomputing: Methodology and Applications

Heat dissipation is a critical challenge facing the realization of emerging nanocomputing technologies. There are different components of this dissipation, and a part of it comes from the unavoidable cost of implementing logically irreversible operations. This stems from the fact that information is physical and manipulating it irreversibly requires energy. The unavoidable dissipative cost of losing information irreversibly fixes the fundamental limit on the minimum energy cost for computational strategies that utilize ubiquitous irreversible information processing. A relation between the amount of irreversible information loss in a circuit and the associated energy dissipation was formulated by Landauer\u27s Principle in a technology-independent form. In a computing circuit, in addition to the nformation-theoretic dissipation, other physical processes that take place in association with irreversible information loss may also have an unavoidable thermodynamic cost that originates from the structure and operation of the circuit. In conventional CMOS circuits such unavoidable costs constitute only a minute fraction of the total power budget, however, in nanocircuits, it may be of critical significance due to the high density and operation speeds required. The lower bounds on energy, when obtained by considering the irreversible information cost as well as unavoidable costs associated with the operation of the underlying computing paradigm, may provide insight into the fundamental limitations of emerging technologies. This motivates us to study the problem of determining heat dissipation of computation in a way that reveals fundamental lower bounds on the energy cost for circuits realized in new computing paradigms. In this work, we propose a physical-information-theoretic methodology that enables us to obtain such bounds for the minimum energy requirements of computation for concrete circuits realized within specific paradigms, and illustrate its application via prominent nanacomputing proposals. We begin by introducing the unavoidable heat dissipation problem and emphasize the significance of limitations it imposes on emerging technologies. We present the methodology developed to obtain the lower bounds on the unavoidable dissipation cost of computation for nanoelectronic circuits. We demonstrate our methodology via its application to various non-transistor-based (e.g. QCA) and transistor-based (e.g. NASIC) nanocomputing circuits. We also employ two CMOS circuits, in order to provide further insight into the application of our methodology by using this well-known conventional paradigm. We expand our methodology to modularize the dissipation analysis for QCA and NASIC paradigms, and discuss prospects for automation. We also revisit key concepts in thermodynamics of computation by focusing on the criticisms raised against the validity of Landauer\u27s Principle. We address these arguments and discuss their implications for our methodology. We conclude by elaborating possible directions towards which this work can be expanded

Ab initio Molecular Dynamics Simulations of Field-Coupled Nanocomputing Molecules

Molecular Field-Coupled Nanocomputing (FCN) represents one of the most promising solutions to overcome the issues introduced by CMOS scaling. It encodes the information in the molecule charge distribution and propagates it through electrostatic intermolecular interaction. The need for charge transport is overcome, hugely reducing power dissipation. At the current state-of-the-art, the analysis of molecular FCN is mostly based on quantum mechanics techniques, or ab initio evaluated transcharacteristics. In all the cases, studies mainly consider the position of charges/atoms to be fixed. In a realistic situation, the position of atoms, thus the geometry, is subjected to molecular vibrations. In this work, we analyse the impact of molecular vibrations on the charge distribution of the 1,4-diallyl butane. We employ Ab Initio Molecular Dynamics to provide qualitative and quantitative results which describe the effects of temperature and electric fields on molecule charge distribution, taking into account the effects of molecular vibrations. The molecules are studied at near-absolute zero, cryogenic and ambient temperature conditions, showing promising results which proceed towards the assessment of the molecular FCN technology as a possible candidate for future low-power digital electronics. From a modelling perspective, the diallyl butane demonstrates good robustness against molecular vibrations, further confirming the possibility to use static transcharacteristics to analyse molecular circuits

Hybrid Quantum-Dot Cellular Automata Nanocomputing Circuits

Quantum-dot cellular automata (QCA) is an emerging transistor-less field-coupled nanocomputing (FCN) approach to ultra-scale ‘nanochip’ integration. In QCA, to represent digital circuitry, electrostatic repulsion between electrons and the mechanism of electron tunnelling in quantum dots are used. QCA technology can surpass conventional complementary metal oxide semiconductor (CMOS) technology in terms of clock speed, reduced occupied chip area, and energy efficiency. To develop QCA circuits, irreversible majority gates are typically used as the primary components. Recently, some studies have introduced reversible design techniques, using reversible majority gates as the main building block, to develop ultra-energy-efficient QCA circuits. However, this approach resulted in time delays, an increase in the number of QCA cells used, and an increase in the chip area occupied. This work introduces a novel hybrid design strategy employing irreversible, reversible, and partially reversible QCA gates to establish an optimal balance between power consumption, delay time, and occupied area. This hybrid technique allows the designer to have more control over the circuit characteristics to meet different system needs. A combination of reversible, irreversible, and innovative partially reversible majority gates is used in the proposed hybrid design method. We evaluated the hybrid design method by examining the half-adder circuit as a case study. We developed four hybrid QCA half-adder circuits, each of which simultaneously incorporates various types of majority gates. The QCADesigner-E 2.2 simulation tool was used to simulate the performance and energy efficiency of the half-adders. This tool provides numerical results for the circuit input/output response and heat dissipation at the physical level within a microscopic quantum mechanical model.N/

Exploration of Majority Logic Based Designs for Arithmetic Circuits

Since its inception, Moore\u27s Law has been a reliable predictor of computational power. This steady increase in computational power has been due to the ability to fit increasing numbers of transistors in a single chip. A consequence of increasing the number of transistors is also increasing the power consumption. The physical properties of CMOS technologies will make this powerwall unavoidable and will result in severe restrictions to future progress and applications. A potential solution to the problem of rising power demands is to investigate alternative low power nanotechnologies for implementing logic circuits. The intrinsic properties of these emerging nanotechnologies result in them being low power in nature when compared to current CMOS technologies. This thesis specifically highlights quantum dot celluar automata (QCA) and nanomagnetic logic (NML) as just two possible technologies. Designs in NML and QCA are explored for simple arithmetic units such as full adders and subtractors. A new multilayer 5-input majority gate design is proposed for use in NML. Designs of reversible adders are proposed which are easily testable for unidirectional stuck at faults

SCERPA: a Self-Consistent Algorithm for the Evaluation of the Information Propagation in Molecular Field-Coupled Nanocomputing

Among the emerging technologies that are intended to outperform the current CMOS technology, the field-coupled nanocomputing (FCN) paradigm is one of the most promising. The molecular quantum-dot cellular automata (MQCA) has been proposed as possible FCN implementation for the expected very high device density and possible room temperature operations. The digital computation is performed via electrostatic interactions among nearby molecular cells, without the need for charge transport, extremely reducing the power dissipation. Due to the lack of mature analysis and design methods, especially from an electronics standpoint, few attempts have been made to study the behavior of logic circuits based on real molecules, and this reduces the design capability. In this article, we propose a novel algorithm, named self-consistent electrostatic potential algorithm (SCERPA), dedicated to the analysis of molecular FCN circuits. The algorithm evaluates the interaction among all molecules in the system using an iterative procedure. It exploits two optimizations modes named Interaction Radius and Active Region which reduce the computational cost of the evaluation, enabling SCERPA to support the simulation of complex molecular FCN circuits and to characterize consequentially the technology potentials. The proposed algorithm fulfills the need for modeling the molecular structures as electronic devices and provides important quantitative results to analyze the information propagation, motivating and supporting further research regarding molecular FCN circuits and eventual prototype fabrication

Design and Investigation of Genetic Algorithmic and Reinforcement Learning Approaches to Wire Crossing Reductions for pNML Devices

Perpendicular nanomagnet logic (pNML) is an emerging post-CMOS technology which encodes binary data in the polarization of single-domain nanomagnets and performs operations via fringing field interactions. Currently, there is no complete top-down workflow for pNML. Researchers must instead simultaneously handle place-and-route, timing, and logic minimization by hand. These tasks include multiple NP-Hard subproblems, and the lack of automated tools for solving them for pNML precludes the design of large-scale pNML circuits

A Novel Reconfiguration Scheme in Quantum-Dot Cellular Automata for Energy Efficient Nanocomputing

Quantum-Dot Cellular Automata (QCA) is currently being investigated as an alternative to CMOS technology. There has been extensive study on a wide range of circuits from simple logical circuits such as adders to complex circuits such as 4-bit processors. At the same time, little if any work has been done in considering the possibility of reconfiguration to reduce power in QCA devices. This work presents one of the first such efforts when considering reconfigurable QCA architectures which are expected to be both robust and power efficient. We present a new reconfiguration scheme which is highly robust and is expected to dissipate less power with respect to conventional designs. An adder design based on the reconfiguration scheme will be presented in this thesis, with a detailed power analysis and comparison with existing designs. In order to overcome the problems of routing which comes with reconfigurability, a new wire crossing mechanism is also presented as part of this thesis

Comparative Study on Performance and Variation Tolerance of Low Power Circuit

The demand for low-power electronic devices is increasing rapidly in current VLSI technology. Instead of conventional CMOS circuit operating at nominal supply voltage, several kinds of circuits are brought about with the goal of reducing power consumption. This research is mainly focused on evaluating performance, power and variation tolerance of near/sub-threshold computing and adiabatic logic circuits. Arithmetic logic units (ALUs) are designed with 15nm FinFET process technologies for these circuit styles. The evaluation is carried out by simulations on these ALU designs. The variation model considers ambient temperature variations and power supply fluctuations that emulate wireless sensor node applications. The results shows that conventional static CMOS circuit operating in near-threshold region exhibits similar power efficiency with adiabatic logic circuit operating in the same region, while at the same time it bears better temperature and voltage variation tolerance in most of the cases. The study results provide helpful guidance to low-power electronic system designs