Symbol Synchronization for SDR Using a Polyphase Filterbank Based on an FPGA

This paper is devoted to the proposal of a highly efficient symbol synchronization subsystem for Software Defined Radio. The proposed feedback phase-locked loop timing synchronizer is suitable for parallel implementation on an FPGA. The polyphase FIR filter simultaneously performs matched-filtering and arbitrary interpolation between acquired samples. Determination of the proper sampling instant is achieved by selecting a suitable polyphase filterbank using a derived index. This index is determined based on the output either the Zero-Crossing or Gardner Timing Error Detector. The paper will extensively focus on simulation of the proposed synchronization system. On the basis of this simulation, a complete, fully pipelined VHDL description model is created. This model is composed of a fully parallel polyphase filterbank based on distributed arithmetic, timing error detector and interpolation control block. Finally, RTL synthesis on an Altera Cyclone IV FPGA is presented and resource utilization in comparison with a conventional model is analyzed

Fractionally-addressed delay lines

While traditional implementations of variable-length digital delay lines are based on a circular buffer accessed by two pointers, we propose an implementation where a single fractional pointer is used both for read and write operations. On modern general-purpose architectures, the proposed method is nearly as efficient as the popularinterpolated circular buffer, and it behaves well for delay-length modulations commonly found in digital audio effects. The physical interpretation of the new implementation shows that it is suitable for simulating tension or density modulations in wave-propagating media.Comment: 11 pages, 19 figures, to be published in IEEE Transactions on Speech and Audio Processing Corrected ACM-clas

Noise shaping Asynchronous SAR ADC based time to digital converter

Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin

Design and Validation of a Software Defined Radio Testbed for DVB-T Transmission

This paper describes the design and validation of a Software Defined Radio (SDR) testbed, which can be used for Digital Television transmission using the Digital Video Broadcasting - Terrestrial (DVB-T) standard. In order to generate a DVB-T-compliant signal with low computational complexity, we design an SDR architecture that uses the C/C++ language and exploits multithreading and vectorized instructions. Then, we transmit the generated DVB-T signal in real time, using a common PC equipped with multicore central processing units (CPUs) and a commercially available SDR modem board. The proposed SDR architecture has been validated using fixed TV sets, and portable receivers. Our results show that the proposed SDR architecture for DVB-T transmission is a low-cost low-complexity solution that, in the worst case, only requires less than 22% of CPU load and less than 170 MB of memory usage, on a 3.0 GHz Core i7 processor. In addition, using the same SDR modem board, we design an off-line software receiver that also performs time synchronization and carrier frequency offset estimation and compensation

A FRACTIONAL DELAY FIR FILTER BASED ON LAGRANGE INTERPOLATION OF FARROW STRUCTURE

An efficient implementation technique for the Lagrange interpolation is derived. This formulation called the Farrow structure leads to a version of Lagrange interpolation that is well suited to time varying FD filtering. Lagrange interpolation is mostly used for fractional delay approximation as it can be used for increasing the sampling rate of signals and systems. Lagrange interpolation is one of the representatives for a class of polynomial interpolation techniques. The computational cost of this structure is reduced as the number of multiplications are minimised in the new structure when compared with the conventional structure

Digital resampling and timing recovery in QAM systems

Digital resampling is a process that converts a digital signal from one sampling rate to another. This process is performed by means of interpolating between the input samples to produce output samples at an output sampling rate. The digital interpolation process is accomplished with an interpolation filter. The problem of resampling digital signals at an output sampling rate that is incommensurate with the input sampling rate is the first topic of this thesis. This problem is often encountered in practice, for example in multiplexing video signals from different sources for the purpose of distribution. There are basically two approaches to resample the signals. Both approaches are thoroughly described and practical circuits for hardware implementation are provided. A comparison of the two circuits shows that one circuit requires a division to compute the new sampling times. This time scaling operation adds complexity to the implementation with no performance advantage over the other circuit, and makes the 'division free' circuit the preferred one for resampling. The second topic of this thesis is performance analysis of interpolation filters for Quadrature Amplitude Modulation (QAM) signals in the context of timing recovery. The performance criterion of interest is Modulation Error Ratio (MER), which is considered to be a very useful indicator of the quality of modulated signals in QAM systems. The methodology of digital resampling in hardware is employed to describe timing recovery circuits and propose an approach to evaluate the performance of interpolation filters. A MER performance analysis circuit is then devised. The circuit is simulated with MATLAB/Simulink as well as implemented in Field Programmable Gate Array (FPGA). Excellent agreement between results obtained from simulation and hardware implementation proves the validity of the methodology and practical application of the research works

Causal Instrument Corrections for Short-Period and Broadband Seismometers

Of all the filters applied to recordings of seismic waves, which include source, path, and site effects, the one we know most precisely is the instrument filter. Therefore, it behooves seismologists to accurately remove the effect of the instrument from raw seismograms. Applying instrument corrections allows analysis of the seismogram in terms of physical units (e.g., displacement or particle velocity of the Earth’s surface) instead of the output of the instrument (e.g., digital counts). The instrument correction can be considered the most fundamental processing step in seismology since it relates the raw data to an observable quantity of interest to seismologists. Complicating matters is the fact that, in practice, the term “instrument correction” refers to more than simply the seismometer. The instrument correction compensates for the complete recording system including the seismometer, telemetry, digitizer, and any anti‐alias filters

Wideband Time-Domain Digital Backpropagation via Subband Processing and Deep Learning

We propose a low-complexity sub-banded DSP architecture for digital backpropagation where the walk-off effect is compensated using simple delay elements. For a simulated 96-Gbaud signal and 2500 km optical link, our method achieves a 2.8 dB SNR improvement over linear equalization.Comment: 3 pages, 3 figur

Signal processing with frequency and phase shift keying modulation in telecommunications

In this paper represents research improving effectiveness of signal processing in telecommunication devices especially for its part, which relates to providing its noise resistance in conditions of noise and interference. This objective has been achieved through development of methods and means for optimization of filtering devices and semigraphical interpretation of clock synchronization systems in telecommunications with frequency shift keying on the base of stochastic models what determines relevance of the subject. Separately, in an article considered the urgent task is using of modified synchronization methods based on the interference influence of adjacent symbols on the phase criterion tract, in particular the use of the modified synchronization scheme, in order to get a formalized outlook representation of the synchronization schemas based on the polyphase structures with using a bank of filters, that allows to improve the characteristics of digital telecommunication channels. This work is devoted to the examination and modeling of these ways. The proposed ideas and results for the construction of synchronization systems can be used in modern means of telecommunication